ATTINY15L-1PC Atmel, ATTINY15L-1PC Datasheet - Page 49
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ATTINY15L-1PC
Manufacturer Part Number
ATTINY15L-1PC
Description
IC AVR MCU 1K FLASH 2.7V 8DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY15L-1PC
Core Processor
AVR
Core Size
8-Bit
Speed
1.6MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Ram Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
The ADC Data Register –
ADCL and ADCH
ADLAR = 0
ADLAR = 1
Scanning Multiple Channels
1187H–AVR–09/07
When an ADC conversion is complete, the result is found in these two registers. When
ADCL is read, the ADC Data Register is not updated until ADCH is read. If the result is
left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH.
Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX affects the
way the result is read from the registers. If ADLAR is set, the result is left-adjusted. If
ADLAR is cleared (default), the result is right-adjusted.
• ADC9..0: ADC Conversion Result
These bits represent the result from the conversion. For the differential channel, this is
the value after gain adjustment, as indicated in Table 20 on page 47. For single-ended
conversion, or if ADLAR or SIGN is zero, $000 represents ground and $3FF represents
the selected reference voltage minus one LSB.
Since change of analog channel always is delayed until a conversion is finished, the
Free Running mode can be used to scan multiple channels without interrupting the con-
verter. Typically, the ADC Conversion Complete Interrupt will be used to perform the
channel shift. However, the user should take the following fact into consideration:
Bit
$05
$04
Read/Write
Initial Value
Bit
$05
$04
Read/Write
Initial Value
The interrupt triggers once the result is ready to be read. In Free Running mode, the
next conversion will start immediately when the interrupt triggers. If ADMUX is
changed after the interrupt triggers, the next conversion has already started, and the
old setting is used.
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
–
6
0
0
6
0
0
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
ADC9
ADC1
ADC3
R
R
R
R
9
1
0
0
9
–
1
0
0
ATtiny15L
ADC8
ADC0
ADC2
R
R
R
R
8
0
0
0
8
–
0
0
0
ADCH
ADCL
ADCH
ADCL
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