ATTINY15L-1PC Atmel, ATTINY15L-1PC Datasheet - Page 15
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ATTINY15L-1PC
Manufacturer Part Number
ATTINY15L-1PC
Description
IC AVR MCU 1K FLASH 2.7V 8DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY15L-1PC
Core Processor
AVR
Core Size
8-Bit
Speed
1.6MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Ram Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Power-on Reset
1187H–AVR–09/07
Table 5. Reset Delay Selections
Notes:
Table 5 shows the start-up times from Reset. When the CPU wakes up from Power-
down, only the clock-counting part of the start-up time is used. The Watchdog Oscillator
is used for timing the real-time part of the start-up time. The number Watchdog Oscilla-
tor cycles used for each time-out is shown in Table 6.
The frequency of the Watchdog Oscillator is voltage dependent as shown in the Electri-
cal Characteristics section on page 64. The device is shipped with CKSEL = “00”.
Table 6. Number of Watchdog Oscillator Cycles
A Power-on Reset (POR) pulse is generated by an On-chip Detection circuit. The detec-
tion level is nominally defined in Table 4. The POR is activated whenever V
the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-
mines the delay, for which the device is kept in RESET after V
period of the delay counter can be defined by the user through the CKSEL Fuses. The
different selections for the delay period are presented in Table 5. The RESET signal is
activated again, without any delay, when the V
BODEN
x
x
x
1
0
1. On Power-up, the start-up time is increased with typical 0.6 ms.
2. “0” means programmed, “1” means unprogrammed.
V
(2)
CC
Conditions
CKSEL [1:0]
2.7V
2.7V
2.7V
2.7V
5.0V
5.0V
5.0V
5.0V
00
01
10
11
11
(2)
t
TOUT
256 ms + 18 CK
256 ms + 18 CK
18 CK + 128 µs
Start-up Time,
16 ms + 18 CK
18 CK + 32 µs
(1)
at V
Time-out
256 ms
128 µs
CC
16 ms
64 ms
32 µs
32 µs
4 ms
8 µs
= 2.7V
CC
decreases below detection level.
t
TOUT
Start-up Time,
64 ms + 18 CK
64 ms + 18 CK
18 CK + 32 µs
4 ms + 18 CK
18 CK + 8 µs
at V
CC
= 5.0V
Number of Cycles
CC
64K
64K
ATtiny15L
32
4K
32
4K
rise. The Time-out
8
8
Recommended
Usage
BOD disabled,
slowly rising
power
BOD disabled,
slowly rising
power
BOD disabled,
quickly rising
power
BOD disabled
BOD enabled
CC
is below
15