AT91M63200-25AI Atmel, AT91M63200-25AI Datasheet - Page 8

• Manufacturer Part Number: AT91M63200-25AI
• Description: IC ARM7 MCU 176 TQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M63200-25AI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-TQFP, 176-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TC: Timer/Counter
The AT91M63200 features two identical Timer/Counter
blocks, each containing three identical 16-bit timer counter
c h a n n e l s . E a c h c h a n n e l c a n b e i n d e p e n d e n t l y
programmed to perform a wide range of functions,
including frequency measurement, event counting, interval
measurement, pulse generation, delay timing and pulse-
width modulation.
Each Timer/Counter channel has three external clock
inputs, five internal clock inputs, and two multi-purpose
input/output signals that can be configured by the user.
Each channel drives an internal interrupt signal that can be
programmed to generate processor interrupts via the
Advanced Interrupt Controller (AIC).
Each Timer Counter block features two global registers that
act upon all three TC channels. The Block Control Register
allows the three channels to be started simultaneously with
the same instruction. The Block Mode Register defines the
external clock inputs for each Timer/Counter channel,
allowing them to be chained.
WD: Watchdog Timer
The AT91M63200 features an internal watchdog timer,
which can be used to guard against system lock-up if the
software becomes trapped in a deadlock.
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AT91M63200
PMC: Power Management Controller
The Power Management Controller allows optimization of
power consumption. The PMC enables/disables the clock
inputs to most of the peripherals as well as to the ARM pro-
cessor core.
When the ARM core clock is disabled, the current instruc-
tion is processed before the clock is stopped. The clock
can be re-enabled by any enabled interrupt or by a hard-
ware reset.
When a peripheral clock is disabled, the clock is immedi-
ately stopped. When the clock is re-enabled, the peripheral
resumes action where it left off.
Due to the static nature of the design, the contents of the
on-chip RAM and registers for which the clocks are dis-
abled remain unchanged.
SF: Special Function
The AT91M63200 provides registers that implement the
following special functions:
• Chip identification
• RESET status