SAK-TC1796-256F150E BE Infineon Technologies, SAK-TC1796-256F150E BE Datasheet - Page 40

• Manufacturer Part Number: SAK-TC1796-256F150E BE
• Description: IC MCU 32BIT FLASH 416-BGA
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1796-256F150E BE

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: ASC, CAN, EBI/EMI, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 123
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 44x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 416-BGA
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: ASC, JTAG, MLI, MSC, SSC
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 260
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel) / 10 bit, 4 Channel
• Packages: P-BGA-416
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 256.0 KByte
• Can Nodes: 4
• A / D Input Lines (incl. Fadc): 44
• Program Memory: 2.0 MB
• For Use With: B158-H8537-G2-X-7600IN - KIT STARTER TC179X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000438972

TC1796
Functional Description
3.4
Memory Protection System
The TC1796 memory protection system specifies the addressable range and read/write
permissions of memory segments available to the currently executing task. The memory
protection system controls the position and range of addressable segments in memory.
It also controls the kinds of read and write operations allowed within addressable
memory segments. Any illegal memory access is detected by the memory protection
hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the
error. Thus, the memory protection system protects critical system functions against both
software and hardware errors. The memory protection hardware can also generate
signals to the Debug Unit to facilitate tracing illegal memory accesses.
There are two Memory Protection Register Sets in the TC1796, numbered 0 and 1,
which specify memory protection ranges and permissions for code and data. The
PSW.PRS bit field determines which of these is the set currently in use by the CPU.
Because the TC1796 uses a Harvard-style memory architecture, each Memory
Protection Register Set is broken down into a Data Protection Register Set and a Code
Protection Register Set. Each Data Protection Register Set can specify up to four
address ranges to receive particular protection modes. Each Code Protection Register
Set can specify up to two address ranges to receive particular protection modes.
Each of the Data Protection Register Sets and Code Protection Register Sets
determines the range and protection modes for a separate memory area. Each contains
register pairs which determine the address range (the Data Segment Protection
Registers and Code Segment Protection Registers) and one register (Data Protection
Mode Register) which determines the memory access modes which apply to the
specified range.
Data Sheet
40
V1.0, 2008-04