SAK-TC1767-256F133HL AD Infineon Technologies, SAK-TC1767-256F133HL AD Datasheet - Page 109

• Manufacturer Part Number: SAK-TC1767-256F133HL AD
• Description: IC MCU 32BIT FLASH 176-LQFP
• Manufacturer: Infineon Technologies
• Series: TC17xxr

Specifications of SAK-TC1767-256F133HL AD

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 88
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 4x10b, 32x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 176-LFQFP
• Data Bus Width: 32 bit
• Data Ram Size: 92 KB
• Interface Type: SPI
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (12 bit, 16 Channel)
• Packages: PG-LQFP-176
• Max Clock Frequency: 133.0 MHz
• Sram (incl. Cache): 128.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 2.0 MB
• For Use With: B158-H8539-G2-X-7600IN - KIT STARTER TC176X SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000458056

2)
3) Any ESR0 activation is internally prolonged to SCU_RSTCNTCON.RELSA FPI bus clock (
4) Applicable for input pins TESTMODE and TRST.
5)
6) Not subject to production test, verified by design / characterization.
7) This parameter includes the delay of the analog spike filter in the PORST pad.
8) The duration of the boot-time is defined between the rising edge of the PORST and the moment when the first
9) The duration of the boot time is defined between the rising edge of the internal application reset and the clock
10) The given time includes the time of the internal reset extension for a configured value of
Figure 25
Data Sheet
TESTMODE
t
0,3 ×
optimized by the customer and checked for negative resistance as recommended and specified by crystal
suppliers.
f
user instruction has entered the CPU and its processing starts.
cycle when the first user instruction has entered the CPU pipeline and its processing starts.
SCU_RSTCNTCON.RELSA = 0x05BE.
OSCS
FPI
HWCFG
PORST
=
VDDP
TRST
ESR0
Pads
VDD
is defined from the moment when
V
f
CPU
DDOSC3
V
D D PPA
/ 2
. This parameter is verified by device characterization. The external oscillator circuitry must be
Power, Pad and Reset Timing
Pad-state undefined
Tri-state or pull device active
As programmed
t
POA
t
POA
t
hd
t
PIP
t
POH
t
t
HDH
PI
V
DDOSC3
t
PIP
= 3.13 V until the oscillations reach an amplitude at XTAL1 of
t
PI
105
t
hd
t
PIP
t
POH
t
t
HDH
PI
t
t
HDH
PI
Electrical Parameters
t
PI
V
D D
-12%
f
FPI
V1.3, 2009-09
) cycles.
TC1767
V
D D P
V
reset_beh2
D D PPA
-12%