SAF-TC1164-128F80HL AB Infineon Technologies, SAF-TC1164-128F80HL AB Datasheet - Page 53

• Manufacturer Part Number: SAF-TC1164-128F80HL AB
• Description: IC MCU 32BIT FLASH LQFP176-2
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1164-128F80HL AB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 76K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 36x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 76.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Preliminary
3.6
The DMA Controller of the TC1163/TC1164 transfers data from data source locations to
data destination locations without intervention of the CPU or other on-chip devices. One
data move operation is controlled by one DMA channel. Eight DMA channels are
provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA
Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the
TC1163/TC1164, the FPI Bus interfaces are connected to the System Peripheral Bus
and the DMA Bus. The third specific bus interface provides a connection to Micro Link
Interface modules (two MLI modules in the TC1163/TC1164) and other DMA-related
devices (Memory Checker module in the TC1163/TC1164). Clock control, address
decoding, DMA request wiring, and DMA interrupt service request control are
implementation-specific and managed outside the DMA controller kernel.
shows the implementation details and interconnections of the DMA module.
Figure 3-2
Data Sheet
Requests
Address
Decoder
Interrupt
Request
On-chip
Control
Periph.
Nodes
Clock
DMA
Units
of
DMA Controller and Memory Checker
SR[15:0]
DMA Controller Block Diagram
f
DMA
CH0n_OUT
Selection/
Arbitration
Request
DMA Interrupt Control
DMA Sub-Block 0
DMA Controller
Control Unit
Transaction
Channels
00-07
DMA
49
Arbiter/
Control
Switch
Switch
Bus
TC1163/TC1164 DMA Block Diagram
Functional Description
TC1163/TC1164
V1.0, 2008-04
System
Periphera
Bus
DMA Bus
Memory
Checker
Figure 3-2
MLI0