SAF-TC1164-128F80HL AB Infineon Technologies, SAF-TC1164-128F80HL AB Datasheet - Page 29

• Manufacturer Part Number: SAF-TC1164-128F80HL AB
• Description: IC MCU 32BIT FLASH LQFP176-2
• Manufacturer: Infineon Technologies
• Series: TC116xr

Specifications of SAF-TC1164-128F80HL AB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: ASC, CAN, MLI, MSC, SSC
• Peripherals: DMA, POR, WDT
• Number Of I /o: 81
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 76K x 8
• Voltage - Supply (vcc/vdd): 1.42 V ~ 1.58 V
• Data Converters: A/D 36x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFQFP
• Packages: PG-LQFP-176
• Max Clock Frequency: 80.0 MHz
• Sram (incl. Cache): 76.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 36
• Program Memory: 1.0 MB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Preliminary
3.2
As shown in the TC1163/TC1164 block diagram on
TC1163/TC1164 units provide on-chip memories that are used as program or data
memory.
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• Memory of PCP2
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Features of Program Flash
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Data Sheet
– 12 Kbyte Code Memory (CMEM) with parity error protection
– 8 Kbyte Parameter RAM (PRAM) with parity error protection
Program memory in PMU
– 16 Kbyte Boot ROM (BROM)
– 1024 Kbyte Program Flash (PFlash)
Program memory in PMI
– 8 Kbyte Scratch-Pad RAM (SPRAM)
– 8 Kbyte Instruction Cache (ICACHE)
Data memory in PMU
– 16 Kbyte Data Flash (DFlash)
– 8 Kbyte Overlay RAM (OVRAM)
Data memory in DMI
– 40 Kbyte Local Data RAM (LDRAM)
On-chip SRAM with parity error protection
1024 Kbyte on-chip program Flash memory
Usable for instruction code or constant data storage
256-byte program interface
– 256 bytes are programmed into PFLASH page in one step/command
256-bit read interface
– Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers
Dynamic correction of single-bit errors during read access
Detection of double-bit errors
Fixed sector architecture
– Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte and one 512 Kbyte sectors
– Each sector separately erasable
– Each sector separately write-protectable
Configurable read protection for complete PFLASH with sophisticated read access
supervision, combined with write protection for complete PFLASH (protection against
“Trojan horse” software)
Configurable write protection for each sector
– Each sector separately write-protectable
– With capability to be re-programmed
– With capability to be locked forever (OTP)
Password mechanism for temporary disabling of write and read protection
On-chip generation of programming voltage
On-Chip Memories
25
Page
Functional Description
2-6, some of the
TC1163/TC1164
V1.0, 2008-04