SAF-TC1164-128F80HL AB Infineon Technologies, SAF-TC1164-128F80HL AB Datasheet
SAF-TC1164-128F80HL AB
Specifications of SAF-TC1164-128F80HL AB
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SAF-TC1164-128F80HL AB Summary of contents
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TC1163/TC1164 ...
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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TC1163/TC1164 ...
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... MLI timing, maximum operating frequency limit is extended, t31 is added. 126 Thermal resistance junction leads is updated. Trademarks TriCore® trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
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Preliminary Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary 4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preliminary 1 Summary of Features The TC1163/TC1164 has the following features: • High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit ...
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Preliminary – One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management – One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10- bit, or ...
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... For the available ordering codes for the TC1163/TC1164, please refer to the “Product Catalog Microcontrollers” that summarizes all available microcontroller variants. This document describes the derivatives of the device.The derivatives and summarizes the differences. Table 1-1 TC1163/TC1164 Derivative Synopsis Derivative SAF-TC1163-128F80HL SAF-TC1164-128F80HL Data Sheet Summary of Features Table 1-1 Ambient Temperature Range ...
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Preliminary 2 General Device Information Chapter 2 provides the general information for the TC1163/TC1164. 2.1 Block Diagram Figure 2-1 shows the TC1163/TC1164 block diagram. PMI 8 KB SPRAM 8 KB ICACHE PMU 16 KB BROM 1024 KB Pflash 16 KB ...
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... FCLN0 MSC0 Control SOP0A SON0 AN[35:0] ADC Analog Inputs V DDM V SSM V DDMF V SSMF V ADC/FADC Analog DDAF Power Supply V SSAF V AREF0 V AGND0 V FAREF V FAGND V DDFL3 V Digital Circuitry Power Supply V DDP V 1) Alternate functions for CAN module is not applicable for TC 1163. Figure 2-2 ...
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... OCDSDBG3/OUT43/IN43/P5.3 4 OCDSDBG4/OUT44/IN44/P5.4 5 OCDSDBG5/OUT45/IN45/P5.5 6 OCDSDBG6/OUT46/IN46/P5.6 7 OCDSDBG7/OUT47/IN47/P5.7 8 TRCLK DDP OCDSDBG8/RDATA0B/P5.8 13 OCDSDBG9/RVALID0B/P5.9 14 OCDSDBG10/RREADY0B/P5.10 15 OCDSDBG11/RCLK0B/P5.11 16 OCDSDBG12/TDATA0/P5.12 17 OCDSDBG13/TVALID0B/P5.13 18 OCDSDBG14/TREADY0B/P5.14 19 OCDSDBG15/TCLK0/P5. SSAF V 23 DDAF V 24 DDMF V 25 SSMF V 26 FAREF V 27 FAGND AN35 28 AN34 29 AN33 30 AN32 31 AN31 32 AN30 33 AN29 34 AN28 35 AN7 36 AN27 37 AN26 38 AN25 39 AN24 40 AN23 ...
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Preliminary 2.4 Pad Driver and Input Classes Overview The TC1163/TC1164 provides different types and classes of input and output lines. For understanding of the abbreviations in gives an overview on the pad type and class types. Table 2-1 Pad Driver ...
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Preliminary 2.5 Pin Definitions and Functions Table 2-2 shows the TC1163/TC1164 pin definitions and functions. Table 2-2 Pin Definitions and Functions Symbol Pins I/O Pad Driver Class Parallel Ports P0 I/O A1 P0.0 145 P0.1 146 P0.2 147 P0.3 148 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P1 I P1.4 107 A1 P1.5 108 A1 P1.6 109 A1 P1.7 110 A1 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P2 I ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P2.8 164 A2 P2.9 160 A2 P2.10 161 A2 P2.11 162 A2 P2.12 163 A2 P2.13 165 A1 Data Sheet Power Functions Supply SLSO04 SLSO14 EN00 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P3 I/O P3.0 136 A2 P3.1 135 A2 P3.2 129 A2 P3.3 130 A2 P3.4 132 A2 P3.5 126 A2 P3.6 127 A2 P3.7 131 A2 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P4 I/O P4.[3: Data Sheet Power Functions Supply V Port 4 / Hardware Configuration ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P5 I/O A2 P5.0 1 P5.1 2 P5.2 3 P5.3 4 P5.4 5 P5.5 6 P5.6 7 P5.7 8 Data Sheet Power Functions Supply V Port ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class P5.8 13 P5.9 14 P5.10 15 P5.11 16 P5.12 17 P5.13 18 P5.14 19 P5.15 20 Data Sheet Power Functions Supply OCDSDBG8 RDATA0B OCDSDBG9 RVALID0B OCDSDBG10 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class MSC0 Outputs C FCLP0A 157 O FCLN0 156 O SOP0A 159 O SON0 158 O Data Sheet Power Functions Supply V LVDS MSC Clock and Data ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class Analog Inputs AN[35: AN0 67 AN1 66 AN2 65 AN3 64 AN4 63 AN5 62 AN6 61 AN7 36 AN8 60 AN9 59 AN10 ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class AN31 AN32 31 AN33 30 AN34 29 AN35 28 System I/O TRST 114 I A2 TCK 115 I A2 TDI 111 I A1 ...
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... DDM V 53 – – SSM V 24 – – DDMF V 25 – – SSMF V 23 – – DDAF V 22 – – SSAF V 52 – – AREF0 V 51 – – AGND0 V 26 – – FAREF V 27 – – FAGND V 105 – – DDOSC ...
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Preliminary Table 2-2 Pin Definitions and Functions (cont’d) Symbol Pins I/O Pad Driver Class V 11, – – DDP 69, 83, 100, 124, 154, 171, 139 V 12, – – SS 70, 85, 101, 125, 155, 172, 140 ...
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Preliminary Table 2-3 List of Pull-up/Pull-down Reset Behavior of the Pins Pins All GPIOs, TDI, TMS, TDO HDRST BYPASS TRST, TCK TRCLK BRKIN, BRKOUT, TESTMODE Pull-up NMI, PORST Data Sheet General Device Information PORST = 0 Pull-up Drive-low Pull-up High-impedance ...
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Preliminary 3 Functional Description Chapter 3 provides an overview of the TC1163/TC1164 functional description. 3.1 System Architecture and On-Chip Bus Systems The TC1163/TC1164 has two independent on-chip buses (see also TC1163/TC1164 block diagram on Page 2-6): • Local Memory Bus ...
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Preliminary 3.2 On-Chip Memories As shown in the TC1163/TC1164 block diagram on TC1163/TC1164 units provide on-chip memories that are used as program or data memory. • Program memory in PMU – 16 Kbyte Boot ROM (BROM) – 1024 Kbyte Program ...
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Preliminary • JEDEC-standard based command sequences for PFLASH control – Write state machine controls programming and erase operations – Status and error reporting by status flags and interrupt • Margin check for detection of problematic PFLASH bits Features of Data ...
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Preliminary 3.3 Memory Maps This chapter gives an overview of the TC1163/TC1164 memory map and describes the address locations and access possibilities for the units, memories, and reserved areas as “seen” from different on-chip buses’ (SPB and LMB) point of ...
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Preliminary Table 3-1 TC1163/TC1164 Architectural Address Map (cont’d) Seg- Contents Size ment 14 EXTPER 128 Mbyte CPU[0 ..15 image region Mbyte 15 LMB_PER 256 CSFRs Mbyte INT_PER Data Sheet Functional Description Description Reserved; non-speculative; non-cached; no execution ...
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Preliminary 3.3.2 How to Read the Address Maps The bus-specific address maps describe how the different bus master devices react on accesses to on-chip memories and modules, and which address ranges are valid or invalid for the corresponding buses. The ...
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Preliminary 3.3.3 Contents of the Segments This section summarizes the contents of the segments. Segments 0-7 These segments are reserved segments in the TC1163/TC1164. Segment 8 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows ...
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Preliminary Segment 14 From the SPB point of view (PCP, DMA and Cerberus), this memory segment allows accesses to the PMU Overlay memory (OVRAM), the DMI Local Data RAM (LDRAM), and the PMI scratch-pad RAM (SPRAM). From the CPU point ...
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Preliminary 3.3.4 Address Map of the FPI Bus System Table 3-3 and Table 3-4 3.3.4.1 Segments Table 3-3 shows the address maps of segments seen from the SPB bus masters PCP, ...
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Preliminary Table 3-3 SPB Address Map of Segment (cont’d) Seg- Address Size ment Range 8 8000 0000 - 1 Mbyte H 800F FFFF H ≈ 0.5 8010 0000 - H 8017 7FFF Mbyte H 8017 8000 - ...
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Preliminary Table 3-3 SPB Address Map of Segment (cont’d) Seg- Address Size ment Range 10 A000 0000 - 1 Mbyte H A00F FFFF H ≈ 0.5 A010 0000 - H A017 FFFF Mbyte H A017 8000 - ...
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Preliminary Table 3-3 SPB Address Map of Segment (cont’d) Seg- Address Size ment Range 13 D000 0000 - 40 Kbyte H D000 9FFF H ≈ 64 D000 A000 - H D3FF FFFF Mbyte H D400 0000 - ...
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Preliminary Table 3-3 SPB Address Map of Segment (cont’d) Seg- Address Size ment Range 14 E000 0000 - 128 MB H E7FF FFFF H E800 0000 - 8 Kbyte H E800 1FFF H ≈ 4 E800 2000 ...
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Preliminary 3.3.4.2 Segment 15 Table 3-4 shows the address map of segment 15 as seen from the SPB bus masters PCP, DMA and OCDS. Please note that access address within the defined address range is not automatically ...
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Preliminary Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Port 3 Port 4 Port 5 Reserved Reserved Reserved Reserved Reserved Reserved General Purpose Timer Array 0 (GPTA0) Reserved Reserved Reserved Direct Memory Access Controller (DMA) Reserved MultiCAN Controller ...
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Preliminary Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Reserved Reserved PCP Registers Reserved PCP Data Memory (PRAM) Reserved PCP Code Memory (PCODE) Reserved Reserved Reserved Synchronous Serial Interface 0 (SSC0) Synchronous Serial Interface 1 (SSC1) Fast Analog-to-Digital ...
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Preliminary Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Reserved Micro Link Interface 0 (MLI0) Reserved Memory Checker (MCHK) Reserved MLI0 Small Transfer Windows Reserved Reserved MLI0 Large Transfer Windows Reserved Reserved CPU CPU Slave Interface Registers (CPS) ...
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Preliminary Table 3-4 SPB Address Map of Segment 15 (cont’d) Unit Program Memory Unit (PMU) Reserved Flash Register Reserved Reserved Reserved Reserved Reserved CPU DMI Registers PMI Registers Local Memory Bus Control Unit (LBCU) LFI Bridge Reserved 1) For TC1163, ...
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Preliminary 3.3.5 Address Map of the Local Memory Bus (LMB) Table 3-5 shows the address map as seen from the LMB bus masters (PMI and DMI). Table 3-5 LMB Address Map Seg- Address Size ment Range 1) 0-7 0000 0000 ...
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Preliminary Table 3-5 LMB Address Map (cont’d) Seg- Address Size ment Range 1) 9 9000 0000 - 256 H 9FFF FFFF Mbyte A000 0000 - 1 Mbyte H A00F FFFF H ≈ 0.5 A010 0000 - H ...
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Preliminary Table 3-5 LMB Address Map (cont’d) Seg- Address Size ment Range 1) 12 C000 0000 - 8 Kbyte H C000 1FFF H C000 2000 - 256 H CFFF FFFF Mbyte D000 0000 - 40 Kbyte H ...
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Preliminary Table 3-5 LMB Address Map (cont’d) Seg- Address Size ment Range 15 F000 0000 - 128 H F7FF FFFF Mbyte H F800 0000 - 1 Kbyte H F800 03FF H F800 0400 - 256 byte H F800 04FF H ...
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Preliminary 3.4 Memory Protection System The TC1163/TC1164 memory protection system specifies the addressable range and read/write permissions of memory segments available to the current executing task. The memory protection system controls the position and range of addressable segments in memory. ...
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Preliminary The PCP2 in the TC1163/TC1164 contains an improved version of the TC1775’s PCP with the following enhancements: • Optimized context switching • Support for nested interrupts • Enhanced instruction set • Enhanced instruction execution speed • Enhanced interrupt queueing ...
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Preliminary Table 3-6 PCP2 Instruction Set Overview Instruction Group Description DMA primitives Efficient DMA channel implementation Load/Store Transfer data between PRAM or FPI memory and the general purpose registers, as well as move or exchange values between registers Arithmetic Add, ...
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Preliminary 3.6 DMA Controller and Memory Checker The DMA Controller of the TC1163/TC1164 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled by one ...
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Preliminary Features • 8 independent DMA channels – 8 DMA channels in the DMA Sub-Block – selectable request inputs per DMA channel – 2-level programmable priority of DMA channels within the DMA Sub-Block – Software and hardware ...
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Preliminary Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol. 3.7 Interrupt System The TC1163/TC1164 interrupt system provides a flexible and time-efficient means of processing interrupts. ...
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Preliminary Service Requestors MSC0 MLI0 SSC0 SSC1 ASC0 ASC1 1) MultiCAN ADC0 FADC 38 GPTA0 STM FPU Flash Ext. Int 1) MultiCAN module and the 6 SRNs are not applicable to TC1163. Figure 3-3 Block Diagram of the TC1163/TC1164 Interrupt ...
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Preliminary 3.8 Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) Figure 3-4 shows a global view of the functional blocks and interfaces of the two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. f Clock ASC Control Address Decoder EIR TBIR Interrupt TIR Control RIR ...
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Preliminary selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is ...
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Preliminary 3.9 High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) Figure 3-5 shows a global view of the functional blocks and interfaces of the two high- speed Synchronous Serial Interfaces, SSC0 and SSC1. f SSC 0 Clock f Control C L ...
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Preliminary The SSC supports full-duplex and half-duplex serial synchronous communication up to 40.0 MBaud (@ 80 MHz module clock). The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master ...
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Preliminary 3.10 Micro Second Bus Interface (MSC0) The MSC interface provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream ...
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Preliminary Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Features • Fast synchronous serial interface to connect power switches ...
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Preliminary 3.11 MultiCAN Controller (CAN) Note: Section 3.11 is not applicable to TC1163. Figure 3-7 shows a global view of the MultiCAN module with its functional blocks and interfaces. f CAN Clock f Control CLC Address Decoder Message Object Buffer ...
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Preliminary The bit timings for the CAN nodes are derived from the module timer clock ( are programmable data rate of 1 Mbit/s. External bus transceivers are connected to a CAN node via a pair of receive ...
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Preliminary 3.12 Micro Link Serial Bus Interface (MLI0) The Micro Link Interface is a fast synchronous serial interface that allows data exchange between microcontrollers of the 32-bit AUDO microcontroller family without intervention of a CPU or other bus masters. connected ...
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Preliminary Figure 3-9 shows a global view of the functional blocks of the MLI module with its interfaces Clock Control Address Decoder MLI 0 Module SR[3:0] (Kernel) Interrupt Control SR[4:7] To DMA BRKOUT Cerberus Figure 3-9 Block ...
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Preliminary 3.13 General Purpose Timer Array The GPTA provides a set of timer, compare, and capture functionalities that can be flexibly combined to form signal measurement and signal generation units. They are optimized for tasks typical of electrical motor control ...
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Preliminary 3.13.1 Functionality of GPTA0 The General Purpose Timer Array GPTA0 provides a set of hardware modules required for high-speed digital signal processing: • Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. • Phase Discrimination Logic ...
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Preliminary • Duty Cycle Measurement (DCM) – Four independent units – 100% margin and time-out handling f – maximum resolution GPTA f – /2 maximum input signal frequency GPTA • Digital Phase Locked Loop (PLL) – One unit ...
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Preliminary I/O Sharing Unit • Interconnecting inputs and outputs from internal clocks, FPC, GTC, LTC, ports, and MSC interface Data Sheet Functional Description 66 TC1163/TC1164 V1.0, 2008-04 ...
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Preliminary 3.14 Analog-to-Digital Converter (ADC0) Section 3.14 shows the global view of the ADC module with its functional blocks and interfaces and the features which are provided by the module AGND0 f ADC Clock f Control ...
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Preliminary Features • 8-bit, 10-bit, 12-bit A/D conversion • Conversion time below 2.5µs @ 10-bit resolution • Extended channel status information on request source • Successive approximation conversion method Total Unadjusted Error (TUE) of ±2 LSB @ 10-bit resolution • ...
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Preliminary 3.15 Fast Analog-to-Digital Converter Unit (FADC) The on-chip FADC module of the TC1163/TC1164 basically is a 2-channel A/D converter with 10-bit resolution that operates by the method of the successive approximation. As shown in Figure 3-12, the main FADC ...
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... Channel timer request periods independently selectable for each channel • Selectable, programmable anti-aliasing and data reduction filter block Data Sheet FAREF DDAF DDMF FAGND SSAF SSMF FAIN0P FAIN0N FAIN1P FAIN1N FADC Module Kernel GS[7:0] TS[7:0] PDOUT2 PDOUT3 f clock (262 FADC ...
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Preliminary 3.16 System Timer The TC1163/TC1164’s STM is designed for global system timing applications requiring both high precision and long period. Features • Free-running 56-bit counter • All 56 bits can be read synchronously • Different 32-bit portions of the ...
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Preliminary The STM can also be read in sections from seven registers, STM_TIM0 through STM_TIM6, that select increasingly higher-order 32-bit ranges of the STM. These can be viewed as individual 32-bit timers, each with a different resolution and timing range. ...
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Preliminary STMIR1 Interrupt Control STMIR0 Enable / 00 Disable Clock f 00 Control STM STM_TIM5 Address Decoder PORST Figure 3-13 General Block Diagram of the STM Module Registers Data Sheet 31 23 STM_CMP0 Compare Register 0 31 STM_CMP1 55 47 ...
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Preliminary 3.17 Watchdog Timer The WDT provides a highly reliable and secure way to detect and recover from software or hardware failure. The WDT helps to abort an accidental malfunction of the TC1163/TC1164 in a user-specified time period. When enabled, ...
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Preliminary • Important debugging support is provided through the reset prewarning operation by first issuing an NMI to the CPU before finally resetting the device after a certain period of time. 3.18 System Control Unit The System Control Unit (SCU) ...
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Preliminary 3.19 Boot Options The TC1163/TC1164 booting schemes provide a number of different boot options for the start of code execution. TC1163/TC1164. Table 3-7 TC1163/TC1164 Boot Selections BRKIN HWCFG TESTMODE Type of Boot [3:0] Normal Boot Options 1 0000 1 ...
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Preliminary 3.20 Power Management System The TC1163/TC1164 power management system allows software to configure the various processing units so that they automatically adjust to draw the minimum necessary power for the application. There are three power management modes: • Run ...
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Preliminary enabled interrupt signal is detected, or when the count value (WDT_SR.WDTTIM) changes from 7FFF to 8000 H 3.21 On-Chip Debug Support Figure 3-14 shows a block diagram of the TC1163/TC1164 OCDS system. 16 OCDS2[15:0] TDO TDI TMS TCK TRST ...
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Preliminary OCDS Level 1 Debug Support The OCDS Level 1 debug support is mainly assigned for real-time software debugging purposes which have a demand for low-cost standard debugger hardware. The OCDS Level 1 is based on a JTAG interface that ...
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... Reduces electromagnetic interference (EMI) by switching off unused modules The clock system must be operational before the TC1163/TC1164 can function contains special logic to handle power-up and reset operations. Its services are fundamental to the operation of the entire system contains special fail-safe logic. Features • ...
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Preliminary are derived from f VCO f equal to . CPU XTAL1 f Oscillator OSC Circuit XTAL2 Osc. Run Detect. OGC MOSC OSCR BYPASS Register OSC_CON OSC_ BYPASS Figure 3-15 Clock Generation Unit Recommended Oscillator Circuits The oscillator circuit, a ...
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Preliminary Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the signal ...
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... V SSM SSA (1 (1.5 V) Figure 3-17 Power Supply Concept of TC1163/TC1164 Data Sheet FAR EF (1.5V) (3.3V) (3.3V) (3.3V SSAF AGN D SSMF FAGN FADC ADC Core Flash Ports Memories FL3 (3 TC1163/TC1164 Functional Description 2 TC1163/TC1164 PLL OSC OSC OSC V SSOSC TC1163/TC1164 PwrSupply V1 ...
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Preliminary 3.24 Identification Register Values Table 3-9 shows the address map and reset values of the TC1163/TC1164 Identification Registers. Table 3-9 TC1163/TC1164 Identification Registers Short Name Address SCU_ ID F000 0008 MANID F000 0070 CHIPID F000 0074 RTID F000 0078 ...
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Preliminary 1) The address and reset value of CAN_ID is not applicable to TC1163. Data Sheet Functional Description 85 TC1163/TC1164 V1.0, 2008-04 ...
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Preliminary 4 Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the TC1163/TC1164. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 ...
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Preliminary 4.1.2 Pad Driver and Pad Classes Summary This section gives an overview on the different pad driver classes and its basic characteristics. More details (mainly DC parameters) are defined in Table 4-1 Pad Driver and Pad Classes Overview Class ...
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... V with respect to SS Voltage on any Class D analog input pin with respect V to AGND Voltage on any Class D analog input pin with respect to V SSAF CPU & LMB Bus Frequency FPI Bus Frequency 1) Applicable for DDOSC 2) Applicable for V ...
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Preliminary 4.1.4 Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1163/TC1164. All parameters specified in the following table refer to these operating conditions, unless otherwise noted. Table 4-3 Operating Condition ...
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Preliminary 1) Digital supply voltages applied to the TC1163/TC1164 must be static regulated voltages which allow a typical voltage swing of ±5%. 2) Voltage overshoot permissible at Power-Up and PORST low, provided the pulse duration ...
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Preliminary Table 4-4 Pin Groups for Overload/Short-Circuit Current Sum Parameter Group Pins 1 TRCLK, P5.[7:0], P0.[7:6], P0.[15:14] 2 P0.[13:12], P0.[5:4], P2.[13:8], SOP0A, SON0, FCLP0A, FCLN0 3 P0.[11:8], P0.[3:0], P3.[13:11] 4 P3[10:0], P3.[15:14] 5 HDRST, PORST, NMI, TESTMODE, BRKIN, BRKOUT, BYPASS, ...
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Preliminary 4.2 DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Pins Table 4-5 provides the characteristics of the input/output pins of the TC1163/TC1164. Table 4-5 Input/Output DC-Characteristics (Operating Conditions apply) Parameter Symbol ...
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Preliminary Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol = 3. 3.3V ±5%) V Class A Pads ( DDP Output low V OLA 4) voltage V Output high OHA 3) voltage V Input low voltage ...
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Preliminary Table 4-5 Input/Output DC-Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol I Input leakage OZA24 current Class A2/3/4 pins I Input leakage OZA1 current Class A1 pins = 3. 3.3V ±5%) Class C Pads ( V DDP ...
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Preliminary 4.2.2 Analog to Digital Converter (ADC0) Table 4-6 provides the characteristics of the ADC module in the TC1163/TC1164. Table 4-6 ADC Characteristics (Operating Conditions apply) Parameter Symbol V Analog supply DDM voltage Analog ground SSM voltage ...
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Preliminary Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol t Conversion time C 7) Total unadjusted TUE 5) error 11)5) DNL error TUE DNL 11)5) INL error TUE INL 11)5) Gain error TUE GAIN 11)5) Offset error TUE ...
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Preliminary Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol 14) I Input leakage OZ1 current at analog inputs AN2 to AN30, see Figure 4-3 Input leakage I OZ2 V current at AREF I Input current at AREF 17) ...
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Preliminary Table 4-6 ADC Characteristics (cont’d) (Operating Conditions apply) Parameter Symbol R ON resistance of AIN the transmission gates in the analog voltage path R ON resistance for AIN7T the ADC test (pull-down for AIN7) Current through I AIN7T resistance ...
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Preliminary I 15) is valid for the minimum specified conversion time. The current flowing during an ADC conversion AREF_MAX with a duration 25µs can be calculated with the formula C needs a total charge of ...
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Preliminary R EXT AIN EXT V AREF Figure 4-2 ADC0 Input Circuits Data Sheet R AIN, On ANx C AINTOT V R AGNDx AIN7T Reference Voltage Input Circuitry R V AREF, On AREFx C - AREFTOT V ...
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Preliminary Ioz1 3uA 1uA 400nA 300nA -200nA 2% -1uA Ioz1 3uA 1uA 300nA 200nA -200nA 2% -1uA Figure 4-3 ADC0 Analog Inputs Leakage Data Sheet AN0, AN1 and AN31 95% AN2 to AN30 95% 101 TC1163/TC1164 Electrical Parameters V [V ...
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... CC – ± –1000 300 400 –200 –200 1000 –200 3000 7) SR 3.13 3. 1.42 1.58 SR -0.1 0.1 7)9) SR 3.13 3. SSAF SSAF 0.05V +0.05V FAGND DDMF 102 TC1163/TC1164 Electrical Parameters Unit Remarks Conditions 12) LSB 12) LSB 2) % With calibration, gain Without calibration gain Without calibration ...
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Preliminary Table 4-7 FADC Characteristics (cont’d)(Operating Conditions apply) Parameter Symbol I Analog supply DDMF currents I DDAF I Input current at each FAREF V FAREF I Input leakage current FOZ2 11 FAREF I Input leakage current FOZ3 V ...
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Preliminary 11) This value applies in power-down mode. 12) Not subject to production test, verified by design / characterization. The calibration procedure should run after each power-up, when all power supply voltages and the reference voltage have stabilized. The offset ...
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Preliminary Ioz1 3uA 1uA 400nA 300nA -200nA 2% -1uA Figure 4-5 Analog Inputs AN32-AN35 Leakage Data Sheet AN32 to AN35 95% 98% 105 TC1163/TC1164 Electrical Parameters DDM 100% V1.0, 2008-04 ...
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Preliminary 4.2.4 Oscillator Pins Table 4-8 provides the characteristics of the oscillator pins in the TC1163/TC1164. Table 4-8 Oscillator Pins Characteristics (Operating Conditions apply) Parameter Symbol f Frequency Range OSC Input low voltage XTAL1 Input high voltage ...
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Preliminary 4.2.5 Temperature Sensor Table 4-9 provides the characteristics of the temperature sensor in the TC1163/TC1164. Table 4-9 Temperature Sensor Characteristics (Operating Conditions apply) Parameter Symbol T Temperature SR -40 SR Sensor Range t Start-up time SR TSST after resets ...
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Preliminary 4.2.6 Power Supply Current Table 4-10 provides the characteristics of the power supply current in the TC1163/TC1164. Table 4-10 Power Supply Current (Operating Conditions apply) Parameter Symbol PORST low current PORST low current at ...
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Preliminary 4.3 AC Parameters All AC parameters are defined with the temperature compensation disabled, which means that pads are constantly kept at the maximum strength. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance ...
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Preliminary 4.3.2 Output Rise/Fall Times Table 4-11 provides the characteristics of the output rise/fall times in the TC1163/TC1164. Table 4-11 Output Rise/Fall Times (Operating Conditions apply) Parameter Symbol Class A1 Pads 1) t Rise/fall times , RA1 Class A1 pads ...
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Preliminary 4.3.3 Power Sequencing There is a restriction for the power sequencing of the 3.3 V domain as shown in Figure 4-9. It must always be higher than 1.5 V domain - 0.5 V. The gray area shows the valid ...
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Preliminary V DDP V DDPmin V PORST3 DDmin V PORST1.5min Figure 4-10 Power Down / Power Loss Sequence Data Sheet Power Supply Voltage 3.3V 3.13V PORST 1.5V 1.42V PORST PowerDown3.3_1.5_reset_only_LL.vsd 112 TC1163/TC1164 Electrical Parameters V DDP -5% ...
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Preliminary 4.3.4 Power, Pad and Reset Timing Table 4-12 provides the characteristics of the power, pad and reset timing in the TC1163/TC1164. Table 4-12 Power, Pad and Reset Timing Parameters Parameter V Min. voltage to ensure defined DDP 1) pad ...
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Preliminary 4) Applicable for input pins TESTMODE, TRST, BRKIN, and TXD1A with noise suppression filter of PORST switched-on (BYPASS = 0). 5) The setup/hold values are applicable for Port 0 and Port 4 input pins with noise suppression filter of ...
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Preliminary 4.3.5 Phase Locked Loop (PLL) Section 4.3.5 provides the characteristics of the PLL parameters and its operation in the TC1163/TC1164. Note: All PLL characteristics defined on this and the next page are verified by design characterization. Table 4-13 PLL ...
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Preliminary Note: The frequency of system clock P With rising number of clock cycles the maximum jitter increases linearly value P of that is defined by the K-factor of the PLL. Beyond this value of accumulated jitter ...
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Preliminary Figure 4-13 Approximated Maximum Accumulated PLL Jitter for Typical CPU Clock Frequencies Note: The maximum peak-to-peak noise on the main oscillator and PLL power supply (measured between mV. This condition can be achieved by appropriate ...
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Preliminary 4.3.6 Debug Trace Timing 3.13 to 3.47 V (Class A); SS DDP C C (TRCLK pF; (TR[15:0 Table 4-14 Debug Trace Timing Parameter Parameter TR[15:0] new ...
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Preliminary 4.3.7 Timing for JTAG Signals (Operating Conditions apply, C Table 4-15 TCK Clock Timing Parameter Parameter 1) TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time f 1) should be lower ...
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Preliminary Table 4-16 JTAG Timing Parameter Parameter TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output 2) from TCK TDO valid output ...
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Preliminary TCK TMS TDI TDO Figure 4-16 JTAG Timing Note: The JTAG module is fully compliant with IEEE1149.1-2000 with JTAG clock at 20 MHz. The JTAG clock at 40 MHz is possible with the modified timing diagram shown in Figure ...
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Preliminary 4.3.8 Peripheral Timings Section 4.3.8 provides the characteristics of the peripheral timings in the TC1163/TC1164. Note: Peripheral timing parameters are not subject to production test. They are verified by design/characterization. 4.3.8.1 Micro Link Interface (MLI) Timing Table 4-17 provides ...
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Preliminary TCLKx TDATAx TVALIDx TREADYx RCLKx RDATAx RVALIDx RREADYx MLI Interface Timing Figure 4-17 Note: The generation of RREADYx is in the input clock domain of the receiver. The reception of TREADYx is asynchronous to TCLKx. Data Sheet t 30 ...
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Preliminary 4.3.8.2 Micro Second Channel (MSC) Interface Timing Table 4-18 provides the characteristics of the MSC timing in the TC1163/TC1164. Table 4-18 MSC Interface Timing (Operating Conditions apply, C Parameter 1)2) FCLP clock period SOP/ENx outputs delay from FCLP SDI ...
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Preliminary 4.3.8.3 Synchronous Serial Channel (SSC) Master Mode Timing Table 4-19 provides the characteristics of the SSC timing in the TC1163/TC1164. Table 4-19 SSC Master Mode Timing (Operating Conditions apply, C Parameter 1)2) SCLK clock period MTSR/SLSOx delay from SCLK ...
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Preliminary 5 Package and Reliability Chapter 5 provides the information of the TC1163/TC1164 package and reliability section. 5.1 Package Parameters (PG-LQFP-176-2) Table 5-1 provides the thermal characteristics of the package. Table 5-1 Thermal Characteristics of the Package Parameter Thermal resistance ...
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Preliminary 5.2 Package Outline Figure 5-1 shows the package outlines of the TC1163/TC1164. PG-LQFP-176-2 Plastic Low Profile Quad Flat Package Figure 5-1 Package Outlines PG-LQFP-176-2 You can find all of our packages, sorts of packing and others in our Infineon ...
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Preliminary 5.3 Flash Memory Parameters The data retention time of the TC1163/TC1164’s Flash memory (i.e. the time after which stored data can still be retrieved) depends on the number of times the Flash memory has been erased and programmed. Table ...
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Preliminary 5.4 Quality Declaration Table 5-3 shows the characteristics of the quality parameters in the TC1163/TC1164. Table 5-3 Quality Parameters Parameter ESD susceptibility according to Human Body Model (HBM) ESD susceptibility of the LVDS pins ESD susceptibility according to Charged ...
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