SAB-C161PI-LM 3V CA Infineon Technologies, SAB-C161PI-LM 3V CA Datasheet - Page 71

• Manufacturer Part Number: SAB-C161PI-LM 3V CA
• Description: IC MICROCONTROLLER 16BIT MQFP100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LM 3V CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-MQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B161PILM3VCAXT; SABC161PILM3VCAXT; SP000014365

Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Address hold after
RdCS, WrCS
Data hold after WrCS
1) RW-delay and
2) Read data are latched with the same clock edge that triggers the address change and the rising RD edge.
3) These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
Data Sheet
Therefore address changes before the end of RD have no impact on read cycles.
specified together with the address and signal BHE (see figures below).
A
refer to the next following bus cycle (including an access to an on-chip X-Peripheral).
Symbol
55
57
A
+
CC -16 +
CC 9 +
C
+
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
min.
= 20 MHz
F
69
F
–
–
max.
1 / 2TCL = 1 to 20 MHz
-16 +
TCL - 16
+
Variable CPU Clock
F
min.
F
–
–
max.
&3,
1999-07
Unit
ns
ns