SAB-C161PI-LM 3V CA Infineon Technologies, SAB-C161PI-LM 3V CA Datasheet - Page 57

• Manufacturer Part Number: SAB-C161PI-LM 3V CA
• Description: IC MICROCONTROLLER 16BIT MQFP100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LM 3V CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-MQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B161PILM3VCAXT; SABC161PILM3VCAXT; SP000014365

Multiplexed Bus (Standard Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
Data valid to WR
Data hold after WR
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE fall. edge to RdCS,
WrCS (with RW delay)
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data Sheet
1)
1)
1)
Symbol
22
23
25
27
38
39
40
42
43
44
45
46
47
48
49
A
+
CC 20 +
CC 26 +
CC 26 +
CC 26 +
CC -4 -
CC 46 +
CC 16 +
CC -4 +
CC –
CC –
CC 30 +
CC 50 +
SR –
SR –
SR –
C
+
F
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
min.
= 25 MHz
A
A
55
C
F
F
F
F
A
C
C
–
–
–
–
10 -
40
+
+ 2
–
–
–
0
20
16 +
36 +
–
–
max.
C
A
A
C
C
1 / 2TCL = 1 to 25 MHz
2TCL - 20
+
2TCL - 14
+
2TCL - 14
+
2TCL - 14
+
-4 -
–
3TCL - 14
+
TCL - 4
+
-4
+
–
–
–
–
2TCL - 10
+
3TCL - 10
+
Variable CPU Clock
F
C
F
F
F
A
A
C
C
min.
A
–
–
–
–
10 -
3TCL - 20
+
–
–
–
0
TCL
2TCL - 24
+
3TCL - 24
+
–
–
C
C
C
max.
+ 2
A
A
&3,
1999-07
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns