SAB-C161PI-LM 3V CA Infineon Technologies, SAB-C161PI-LM 3V CA Datasheet - Page 56

• Manufacturer Part Number: SAB-C161PI-LM 3V CA
• Description: IC MICROCONTROLLER 16BIT MQFP100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LM 3V CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-MQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B161PILM3VCAXT; SABC161PILM3VCAXT; SP000014365

Data Sheet
AC Characteristics
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD, WR low time
RD to valid data in
RD to valid data in
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Data float after RD
(no RW-delay)
(with RW-delay)
(no RW-delay)
Symbol
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
+
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC -10 +
CC –
CC –
CC 30 +
CC 50 +
SR –
SR –
SR –
SR –
SR 0
SR –
C
+
F
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
min.
= 25 MHz
A
54
A
A
C
C
A
A
–
–
–
–
–
6
26
–
–
20 +
40 +
40 +
+
50 + 2
+
–
26 +
max.
C
C
C
C
A
F
A
1 / 2TCL = 1 to 25 MHz
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
-10 +
–
–
2TCL - 10
+
3TCL-
10+
–
–
–
–
0
–
Variable CPU Clock
A
A
A
A
C
min.
C
A
–
–
–
–
–
6
TCL + 6
–
–
2TCL - 20
+
3TCL - 20
+
3TCL - 20
+
4TCL - 30
+ 2
–
2TCL - 14
+
C
C
A
F
max.
A
+
+
C
C
&3,
1999-07
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns