SAK-XC2765X-104F80L AA Infineon Technologies, SAK-XC2765X-104F80L AA Datasheet - Page 67

• Manufacturer Part Number: SAK-XC2765X-104F80L AA
• Description: IC MCU 32BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XC27x5Xr

Specifications of SAK-XC2765X-104F80L AA

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 50K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000443762

3.19
Table 11
The addressing modes that can be used with a specific instruction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR/BSET
BMOV(N)
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
BCMP
BFLDH/BFLDL
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL/SHR
Data Sheet
lists the instructions of the XC2765X.
Instruction Set Summary
Instruction Set Summary
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR
(16- × 16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise exclusive OR, (word/byte operands)
Clear/Set direct bit
Move (negated) direct bit to direct bit
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Shift left/right direct word GPR
XC2000 Family Derivatives / Base Line
67
Functional Description
V2.0, 2009-03
XC2765X
2 / 4
2 / 4
2 / 4
2 / 4
2
2 / 4
2 / 4
4
4
2 / 4
2 / 4
Bytes
2
2
2 / 4
2
4
4
2 / 4
2
2