SAK-XC2765X-104F80L AA Infineon Technologies, SAK-XC2765X-104F80L AA Datasheet - Page 49

• Manufacturer Part Number: SAK-XC2765X-104F80L AA
• Description: IC MCU 32BIT FLASH 100-LQFP
• Manufacturer: Infineon Technologies
• Series: XC27x5Xr

Specifications of SAK-XC2765X-104F80L AA

• Core Processor: C166SV2
• Core Size: 16/32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
• Peripherals: I²S, POR, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 50K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LFQFP
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: SP000443762

XC2765X
XC2000 Family Derivatives / Base Line
Functional Description
3.7
On-Chip Debug Support (OCDS)
The On-Chip Debug Support system built into the XC2765X provides a broad range of
debug and emulation features. User software running on the XC2765X can be debugged
within the target system environment.
The OCDS is controlled by an external debugging device via the debug interface. This
either consists of the 2-pin Device Access Port (DAP) or of the JTAG port conforming to
IEEE-1149. The debug interface can be completed with an optional break interface.
The debugger controls the OCDS with a set of dedicated registers accessible via the
debug interface (DAP or JTAG). In addition the OCDS system can be controlled by the
CPU, e.g. by a monitor program. An injection interface allows the execution of OCDS-
generated instructions by the CPU.
Multiple breakpoints can be triggered by on-chip hardware, by software, or by an
external trigger input. Single stepping is supported, as is the injection of arbitrary
instructions and read/write access to the complete internal address space. A breakpoint
trigger can be answered with a CPU halt, a monitor call, a data transfer, or/and the
activation of an external signal.
Tracing data can be obtained via the debug interface, or via the external bus interface
for increased performance.
The DAP interface uses two interface signals, the JTAG interface uses four interface
signals, to communicate with external circuitry. The debug interface can be amended
with two optional break lines.
Data Sheet
49
V2.0, 2009-03