AT89C51ID2-SLRIM Atmel, AT89C51ID2-SLRIM Datasheet - Page 123

• Manufacturer Part Number: AT89C51ID2-SLRIM
• Description: IC MCU FLASH 8051 64K 5V 44-PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ID2-SLRIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: AT89C51ID2SLRIMTR

Bootloader Functionality
Introduction
Figure 48. Hardware conditions typical sequence during power-on.
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AT89C51ID2
The bootloader can be activated by two means: Hardware conditions or regular boot
process.
The Hardware conditions (EA = 1, PSEN = 0) during the Reset# falling edge force the
on-chip bootloader execution. This allows an application to be built that will normally
execute the end user’s code but can be manually forced into default ISP operation.
As PSEN is a an output port in normal operating mode after reset, user application
should take care to release PSEN after falling edge of reset signal. The hardware condi-
tions are sampled at reset signal falling edge, thus they can be released at any time
when reset input is low.
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground
during power-on (See Figure 48).
The on-chip bootloader boot process is shown Figure 49
Hardware Conditions
BLJB
VCC
PSEN
RST
The Hardware Conditions force the bootloader execution whatever BLJB,
BSB and SBV values.
The Boot Loader Jump Bit forces the application execution.
BLJB = 0 => Boot loader execution.
BLJB = 1 => Application execution
The BLJB is a fuse bit in the Hardware Byte.
That can be modified by hardware (programmer) or by software (API).
Note:
The BLJB test is perform by hardware to prevent any program
execution..
Purpose
4289C–8051–11/05