UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 578
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UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.1 Interrupt Function Types
(1) Maskable interrupts
(2) Software interrupt
15.2 Interrupt Sources and Configuration
addition, they also have up to five reset sources (see Table 15-1). The vector codes that store the program start
address when branching due to the generation of a reset or various interrupt requests are two bytes each, so
interrupts jump to a 64 K address of 00000H to 0FFFFH.
576
The following two types of interrupt functions are used.
The 78K0R/KE3 has a total of 39 interrupt sources including maskable interrupts and software interrupts. In
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If
two or more interrupt requests, each having the same priority, are simultaneously generated, then they are
processed according to the priority of vectored interrupt servicing. For the priority order, see Table 15-1.
A standby release signal is generated and STOP and HALT modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts
are disabled. The software interrupt does not undergo interrupt priority control.
External: 13, internal: 25
CHAPTER 15 INTERRUPT FUNCTIONS
User’s Manual U17854EJ9V0UD
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