UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 295
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4.2 Setting overflow time of watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
The following overflow time is set.
Caution The watchdog timer continues its operation during self-programming of the flash memory and
Remarks 1. f
EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the
overflow time and window size taking this delay into consideration.
2. ( ): f
5. The watchdog timer continues its operation during self-programming of the flash memory
WDCS2
IL
depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time
when operating with the X1 oscillation clock and when the watchdog timer is to be cleared
after the STOP mode release by an interval interrupt.
and EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set
the overflow time and window size taking this delay into consideration.
In HALT mode
In STOP mode
0
0
0
0
1
1
1
1
: Internal low-speed oscillation clock frequency
IL
= 264 kHz (MAX.)
WDCS1
Table 8-3. Setting of Overflow Time of Watchdog Timer
0
0
1
1
0
0
1
1
Watchdog timer operation stops.
CHAPTER 8 WATCHDOG TIMER
WDCS0
0
1
0
1
0
1
0
1
User’s Manual U17854EJ9V0UD
WDSTBYON = 0
2
2
2
2
2
2
2
2
10
11
12
13
15
17
18
20
/f
/f
/f
/f
/f
/f
/f
/f
IL
IL
IL
IL
IL
IL
IL
IL
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(124.12 ms)
(496.48 ms)
(992.97 ms)
(3971.88 ms)
Overflow Time of Watchdog Timer
Watchdog timer operation continues.
WDSTBYON = 1
293
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