UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 440
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UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Notes 1. The baud rate is set so as to satisfy the standard of the wakeup signal and data of 00H is transmitted.
Remark
LIN Bus
(output)
INTST3
T
X
D3
2. A sync break field is defined to have a width of 13 bits and output a low level. Where the baud rate for
3. INTST3 is output upon completion of transmission. INTST3 is also output when SBF transmission is
Note 3
main transfer is N [bps], therefore, the baud rate of the sync break field is calculated as follows.
By transmitting data of 00H at this baud rate, a sync break field is generated.
executed.
The interval between fields is controlled by software.
(Baud rate of sync break field) = 9/13 × N
Wakeup signal
8 bits
frame
Note 1
transmission
Figure 11-85. Transmission Operation of LIN
13-bit SBF
Sync break
CHAPTER 11 SERIAL ARRAY UNIT
field
User’s Manual U17854EJ9V0UD
Note 2
transmission
Sync field
55H
Identification
transmission
Data
field
transmission
Data field
Data
transmission
Data field
Data
transmission
Checksum
Data
field
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