UPD78F1142AF1-AN1-A Renesas Electronics America, UPD78F1142AF1-AN1-A Datasheet - Page 181
UPD78F1142AF1-AN1-A
Manufacturer Part Number
UPD78F1142AF1-AN1-A
Description
MCU 16BIT 78K0R/KX3 64-FBGA
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1142AF1-AN1-A
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1142AF1-AN1-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.6.7 Time required for switchover of CPU clock and main system clock
clock can be switched (between the main system clock and the subsystem clock), main system clock can be switched
(between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the main
system clock can be changed.
pre-switchover clock for several clocks (see Table 5-6 to Table 5-9).
(CLS) of CKC. Whether the main system clock is operating on the high-speed system clock or internal high-speed
oscillation clock can be ascertained using bit 5 (MCS) of CKC.
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, MCM0, CSS) of the system clock control register (CKC), the CPU
The actual switchover operation is not performed immediately after rewriting to CKC; operation continues on the
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7
When the CPU clock is switched, the peripheral hardware clock is also switched.
(Remarks are listed on the next page.)
Set Value Before Switchover
Set Value Before Switchover
(f
(f
MAIN
MAIN
Clock A
f
f
MAINC
MAINC
0
1
= f
f
= f
IH
Table 5-6. Maximum Time Required for Main System Clock Switchover
MX
IH
Clock A
Clock B
)
MCM0
)
Table 5-7. Maximum Number of Clocks Required in Type 1
Table 5-8. Maximum Number of Clocks Required in Type 2
f
f
f
f
MX
MX
MX
MX
(Changing the division ratio)
≥f
<f
≥f
<f
IH
IH
IH
IH
Switching directions
CHAPTER 5 CLOCK GENERATOR
1 + f
2f
1 + f
MX
User’s Manual U17854EJ9V0UD
/f
B
MX
IH
/f
/f
A
clock
IH
clock
clock
(f
Clock A
MAIN
0
= f
IH
Set Value After Switchover
Set Value After Switchover
)
Clock B
f
f
SUB
MAINC
f
MCM0
MX
/2
1 + f
1 + f
2f
IH
/f
A
IH
MX
/f
/f
B
MX
clock
clock
clock
Type 1 (see Table 5-7)
Type 2 (see Table 5-8)
Type 3 (see Table 5-9)
(f
MAIN
Clock B
1
= f
MX
Type
)
179
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