UPD78F9222CS-CAC-A Renesas Electronics America, UPD78F9222CS-CAC-A Datasheet - Page 286

• Manufacturer Part Number: UPD78F9222CS-CAC-A
• Description: MCU 8BIT 4KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9222CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

284
(3) Flash status register (PFS)
1. Operating conditions of FPRERR flag
<Setting conditions>
Caution Interrupt servicing cannot be executed in self programming mode.
Caution Check FPRERR using a 1-bit memory manipulation instruction.
<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is
<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal write operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
Check FPRERR using a 1-bit memory manipulation instruction.
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set with an 8-bit memory manipulation instruction.
Reset signal generation makes PFCMD undefined.
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
write a specific value (A5H) to FLPMC
If the first store instruction operation after <1> is on a peripheral register other than FLPMC
If the first store instruction operation after <2> is on a peripheral register other than FLPMC
Address: FFA0H
Address: FFA1H
PFCMD
Symbol
Symbol
invalid)
PFS
servicing (by executing the DI instruction while MK0 and MK1 = FFH) between the points
before executing the specific sequence that sets self programming mode and after executing
the specific sequence that changes the mode to the normal mode.
Figure 18-11. Format of Flash Protect Command Register (PFCMD)
REG7
7
7
0
Figure 18-12. Format of Flash Status Register (PFS)
After reset: Undefined
After reset: 00H
REG6
6
6
0
CHAPTER 18 FLASH MEMORY
REG5
User’s Manual U16898EJ6V0UD
0
5
5
R/W
REG4
W
4
4
0
REG3
3
3
0
WEPRERR
REG2
2
2
VCERR
REG1
1
1
FPRERR
REG0
Disable interrupt
0
0