SAK-XC864L-1FRI 5V AA Infineon Technologies, SAK-XC864L-1FRI 5V AA Datasheet - Page 77

• Manufacturer Part Number: SAK-XC864L-1FRI 5V AA
• Description: IC MCU 8BIT 4KB FLASH 20TSSOP
• Manufacturer: Infineon Technologies
• Series: XC8xxr

Specifications of SAK-XC864L-1FRI 5V AA

• Core Processor: XC800
• Core Size: 8-Bit
• Speed: 86MHz
• Connectivity: LIN, SSI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Table 27
26.67 MHz
13.33 MHz
6.67 MHz
3.11.2
In UART modes 1 and 3, Timer 1 can be used for generating the variable baud rates. In
theory, this timer could be used in any of its modes. But in practice, it should be set into
auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate value for the
required baud rate. The baud rate is determined by the Timer 1 overflow rate and the
value of SMOD as follows:
3.12
Setting bit FDM in register FDCON to 1 configures the fractional divider to normal divider
mode, while at the same time disables baud rate generation (see
fractional divider is enabled (FDEN = 1), it functions as an 8-bit auto-reload timer (with
no relation to baud rate generation) and counts up from the reload value with each input
clock pulse. Bit field RESULT in register FDRES represents the timer value, while bit
field STEP in register FDSTEP defines the reload value. At each timer overflow, an
overflow flag (FDCON.NDOV) will be set and an interrupt request generated. This gives
an output clock
The output frequency in normal divider mode is derived as follows:
Data Sheet
f
PCLK
Baud Rate Generation using Timer 1
Normal Divider Mode (8-bit Auto-reload Timer)
Deviation Error for UART with Fractional Divider enabled
Prescaling Factor
(2
1
1
1
f
MOD
BRPRE
that is 1/n of the input clock
)
Mode 1, 3 baud rate
f
MOD
Reload Value
(BR_VALUE + 1)
7 (7
3 (3
10 (A
=
H
H
f
)
)
DIV
H
73
)
=
---------------------------------------------------- -
32 2
×
----------------------------- -
256 STEP
2
×
f
SMOD
DIV
–
×
, where n is defined by 256 - STEP.
1
(
256 TH1
×
STEP
177 (B1
248 (F8
212 (D4
f
PCLK
–
Functional Description
H
H
H
)
)
)
)
Figure
Deviation
Error
+0.03 %
+0.11 %
-0.16 %
27). Once the
V 1.1, 2009-03
XC864
[7]
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