SAK-XC864L-1FRI 5V AA Infineon Technologies, SAK-XC864L-1FRI 5V AA Datasheet
SAK-XC864L-1FRI 5V AA
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SAK-XC864L-1FRI 5V AA Summary of contents
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XC864 8-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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XC864 8-Bit Single-Chip Microcontroller Data Sheet V1.1 2009- ...
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XC864 Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) Changes from V1.0 2008-08 to V1.1 2009-03 3 Modified the paragraph to remove the Automotive quality profile We Listen to Your Comments Any information within this ...
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Single-Chip Microcontroller XC800 Family 1 Summary of Features • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers • On-chip memory – ...
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... Synchronous serial channel (SSC) • On-chip debug support – 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • PG-TSSOP-20 pin package • Ambient temperature range T – SAF (- °C) – SAK (-40 to 125 °C) Data Sheet : A 2 XC864 Summary of Features ...
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... Table 1-1 summarizes the list of XC864 devices. Table 1-1 Device Profile Sales Type SAK-XC864L-1FRI 5V SAK-XC864L-1FRI 3V3 SAF-XC864L-1FRI 5V SAF-XC864L-1FRI 3V3 Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code identifies: • The derivative itself, i.e. its function set, the temperature range, and the supply voltage • ...
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General Device Information 2.1 Block Diagram XC864 8-Kbyte 1) Boot ROM 256-byte RAM + 64-byte monitor RAM TMS RESET V DDP 512-byte XRAM V DDC V SSC 4-Kbyte Flash Clock Generator 10 MHz On-chip OSC PLL Figure 2 XC864 ...
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Logic Symbol V AREF RESET TMS Figure 3 XC864 Logic Symbol Data Sheet General Device Information DDP SSP AGND XC864 V V DDC SSC 5 XC864 Port 0 6-Bit Port 1 1-Bit Port 2 4-Bit Port ...
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Pin Configuration The pin configuration of the XC864, which is based on the PG-TSSOP-20 package, is shown in Figure 4. Every package pin is bonded to an input port pin or a bidirectional port pin except Pin 15. It ...
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Pin Definitions and Functions Table 1 Pin Definitions and Functions Symbol Pin Type Reset Number P0 I/O P0.0 5 P0.1 7 P0.2 6 P0.3 19 P0.4 20 P0.5 1 Data Sheet Function State Port 0 Port ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P1 I/O P1.0/ 15 P1.1 Data Sheet Function State Port 1 Port 8-bit bidirectional general purpose I/O port. It can be used as alternate functions ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P2 I P2.0 8 P2.1 9 P2.2 10 P2.7 14 Data Sheet Function State Port 2 Port 8-bit general purpose input-only port. It can be ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Type Reset Number P3 I/O P3 – DDP V 3 – DDC V 2 – SSC V 13 – AREF – AGND V ...
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Functional Description 3.1 Processor Architecture The XC864 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC864 ...
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Memory Organization The XC864 consists of four types of memory: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 512 bytes of XRAM memory (XRAM can be read/written as program memory ...
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Memory Protection Strategy The XC864 memory protection strategy includes: • Read-out protection: The user is able to protect the contents in the Flash memory from being read • Flash program and erase protection: The Flash memory in all devices ...
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Table 2 Flash Protection Modes (cont’d) Flash erase Possible, on condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation Additional Block external access (can only start Protection in User Mode) Subsequent Possible entering ...
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Table 3 Password Definition Password To Enable Protection: Type of Hardware Protection 1XXXXXXX Read/Program/Erase B 00001XXX Erase B 00010XXX Erase B 00011XXX Erase B 00100XXX Erase B 00101XXX Erase B 00110XXX Erase B 00111XXX Erase B 01000XXX Erase B 01001XXX ...
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Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range All registers, except the program counter, reside in the SFR area. The H H SFRs include pointers and ...
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Note: The RMAP bit must be cleared/set by ANL or ORL instructions. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, ...
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Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC864 has a 256-SFR address range. However, this is still less than the total number of SFRs ...
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In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access ...
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MOD_PAGE Page Register for module MOD Field Bits PAGE [2:0] STNR [5:4] OP [7:6] Data Sheet STNR Type Description rwh Page Bits When written, the value indicates the new page. ...
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Field Bits 0 3 Data Sheet Type Description r Reserved Returns 0 if read; should be written with 0. 21 XC864 Functional Description V 1.1, 2009-03 ...
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Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access to writing of all protected bits, ...
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XC864 Register Overview The SFRs of the XC864 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in of the bitaddressable SFRs appearing in bold typeface. Note: Bits marked as 0 ...
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Table 4 CPU Register Overview (cont’d) Addr Register Name E0 ACC Reset Accumulator Register IEN1 Reset Interrupt Enable Register Reset Register IP1 Reset Interrupt Priority Register ...
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Table 5 SCU Register Summary (cont’d) Addr Register Name E9 FDCON Reset Fractional Divider Control Register EA FDSTEP Reset Fractional Divider Reload Register EB FDRES Reset Fractional Divider Result Register RMAP = 0, PAGE ...
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Table 6 WDT Register Overview Addr Register Name RMAP = 1 BB WDTCON Reset Watchdog Timer Control Register BC WDTREL Reset Watchdog Timer Reload Register BD WDTWINB Reset Watchdog Window-Boundary Count Register BE WDTL ...
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Table 7 Port Register Overview (cont’d) Addr Register Name A0 P2_PUDSEL Reset Pull-Up/Pull-Down Select Register P2_PUDEN Reset Pull-Up/Pull-Down Enable Register B0 P3_PUDSEL Reset Pull-Up/Pull-Down Select Register B1 P3_PUDEN Reset: 40 ...
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Table 8 ADC Register Overview (cont’d) Addr Register Name CF ADC_ETRCR Reset External Trigger Control Register RMAP = 0, Page 1 CA ADC_CHCTR0 Reset Channel Control Register 0 CB ADC_CHCTR1 Reset Channel Control Register ...
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Table 8 ADC Register Overview (cont’d) Addr Register Name CB ADC_RCR1 Reset Result Control Register 1 CC ADC_RCR2 Reset Result Control Register 2 CD ADC_RCR3 Reset Result Control Register 3 CE ADC_VFCR Reset: 00 ...
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Table 8 ADC Register Overview (cont’d) Addr Register Name D2 ADC_QINR0 Reset Queue Input Register 0 The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 9 Timer 2 Register Overview Addr ...
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Table 10 CCU6 Register Overview (cont’d) Addr Register Name A4 CCU6_ISRL Reset Capture/Compare Interrupt Status Reset Register Low A5 CCU6_ISRH Reset Capture/Compare Interrupt Status Reset Register High A6 CCU6_CMPMODIFL Reset Compare State Modification Register ...
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Table 10 CCU6 Register Overview (cont’d) Addr Register Name A6 CCU6_TCTR0L Reset Timer Control Register 0 Low A7 CCU6_TCTR0H Reset Timer Control Register 0 High FA CCU6_CC60RL Reset Capture/Compare Register for Channel CC60 Low ...
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Table 10 CCU6 Register Overview (cont’d) Addr Register Name FA CCU6_TCTR2L Reset Timer Control Register 2 Low FB CCU6_TCTR2H Reset Timer Control Register 2 High FC CCU6_MODCTRL Reset Modulation Control Register Low FD CCU6_MODCTRH ...
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The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 SSC Register Overview Addr Register Name RMAP = 0 A9 SSC_PISEL Reset Port Input Select Register AA SSC_CONL Reset Control ...
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Table 12 OCDS Register Summary (cont’d) Addr Register Name F4 MMICR Reset Monitor Mode Interrupt Control Register F5 MMDR Reset Monitor Mode Data Transfer Register Receive F6 HWBPSR Reset Hardware Breakpoints Select Register HWBPDR ...
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Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not ...
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Flash Bank Sectorization The XC864 has 4 Kbytes of embedded Flash memory. The Flash bank sectorization is shown in Figure 10. Figure 10 Flash Bank Sectorization The minimum erase width is always a complete sector, and sectors can be ...
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Flash Programming Without Erase The same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. This means if the number of data bytes that needs to be written ...
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In-Application Programming In some applications, the Flash contents may need to be modified during program execution. In-Application Programming (IAP) is supported so that users can program or erase the Flash memory from their Flash user program by calling some ...
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Table 14 Flash Program Subroutin Type 1 (cont’d) Stack size required 12 Resource used/ ACC, B, SCU_PAGE destroyed R0 – Register Bank 3 (IRAM address 18 IRAM address 36 1) The last 5 LSB of the DPL is ...
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Table 15 Flash Program Subroutine Type 2 (cont’d) Resource used/ ACC, B, SCU_PAGE destroyed R0 – Register Bank 3 (IRAM address 18 IRAM address 36 1) The last 5 LSB of the DPL is 0 for an aligned ...
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The inputs should be set the sector(s) of the bank(s) is/are not to be selected for erasing. 2) When Flash Protection Mode 0 is enabled, in order to erase Flash bank, DFLASHEN bit needs to be ...
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Table 17 Flash Erase Subroutine (cont’d)Type 2 Resource used/ ACC, B, SCU_PAGE destroyed R0 – Register Bank 3 (IRAM address 18 IRAM address 36 1) The inputs should be set the sector(s) of the bank(s) ...
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Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt nodes. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the interrupt system provides extended interrupt ...
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Timer 0 Overflow Timer 1 Overflow UART Receive UART Transmit EXINT0 EINT0 IRCON0.0 EXINT0 EXICON0.0/1 EXINT1 EINT1 IRCON0.1 EXINT1 EXICON0.2/3 Bit-addressable Request flag is cleared by hardware Figure 13 Interrupt Request Sources (Part 1) Data Sheet TF0 TCON.5 000B ET0 ...
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Timer 2 Overflow T2EX EXEN2 T2_T2CON.3 EDGES EL Normal Divider T2MOD.5 Overflow End of EOFSYN Synch Byte >=1 FDCON.4 Synch Byte ERRSYN Error FDCON.5 EINT2 EXICON0.4/5 EINT3 EXINT3 EXICON0.6/7 Bit- addressable Request flag is cleared by hardware Figure 14 Interrupt ...
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ADC Service ADCSRC0 Request 0 ADC Service ADCSRC1 Request 1 SSC Error SSC Transmit SSC Receive CCU6 Node 0 CCU6 Node 1 CCU6 Node 2 CCU6 Node 3 Bit-addressable Request flag is cleared by hardware Figure 15 Interrupt Request Sources ...
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ICC60R CC60 ISL.0 ICC60F ISL.1 ICC61R CC61 ISL.2 ICC61F ISL.3 ICC62R CC62 ISL.4 ICC62F ISL.5 T12 T12OM One match ISL.6 T12 T12PM Period match ISL.7 T13 T13CM Compare match ISH.0 T13 T13PM Period match ISH.1 TRPF CTRAP ISH.2 Wrong Hall ...
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Interrupt Source and Vector Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an ...
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Interrupt Priority Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and ...
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Parallel Ports The XC864 has 14 port pins organized into 4 parallel ports, Port 0 (P0) to Port 3 (P3). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports ...
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Px_PUDSEL Internal Bus Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 Px_ALTSEL1 Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 Px_Data Data Register AltDataIn Figure 17 General ...
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Internal Bus AltDataIn AnalogIn Figure 18 General Structure of Input Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register enable In Driver Px_DATA Data Register Schmitt Trigger 53 Functional Description VDDP Pull enable Up Device ...
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Power Supply System with Embedded Voltage Regulator The XC864 microcontroller requires two different levels of power supply: • 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip oscillator, and peripherals ...
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Reset Control The XC864 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC864 is first powered up, the status of certain pins (see defined to ensure proper ...
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Voltage 5V 2.5V 2.3V 0.9*VDDC Voltage 5V < 0.4V 0V typ. < Figure DDP, DDC The second type of reset is the hardware reset. This reset function can be used during normal operation or ...
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Module Reset Behavior Table 20 shows how the functions of the XC864 are affected by the various reset types. A “ ” means that this function is reset to its default state. Table 20 Effect of Reset on Device ...
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Booting Scheme When the XC864 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes ...
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Table 22 Type of Actions related to the NAC value NAC Value 0FF , ...
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NAC values and program an invalid NAC located in address(0FF8 protection mode 0(MSB of PASSWORD selected. When Flash protetcion mode 1(MSB of PASSWORD = 1) is selected, the only way to enter BSL mode is to ...
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Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC864. The power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is directly proportional to the frequency. ...
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PLL Base Mode The system clock is derived from the VCO base (free running) frequency clock divided by the K factor. Prescaler Mode (VCO Bypass Operation) In VCO bypass operation, the system clock is derived from the oscillator clock, divided ...
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For the XC864, the value of P and K are fixed to 1 and 2 respectively. In order to obtain f the required at 80 MHz with a fixed oscillator frequency of 10 MHz, the N factor must sys be ...
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Clock Management The CGU generates all clock signals required within the microcontroller from a single clock During normal system operation, the typical frequencies of the different sys modules are as follow: • CPU clock: CCLK, SCLK = ...
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For power saving purposes, the clocks may be disabled or slowed down according to Table 23. Table 23 System frequency (f Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the ...
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Power Saving Modes The power saving modes of the XC864 provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some ...
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Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must ...
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If the WDT is not serviced before the timer overflow, a system malfunction is assumed result, the WDT NMI is triggered (assert WDTTO) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST). The ...
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Count FFFF H WDTWINB WDTREL Figure 26 WDT Timing Diagram Table 24 lists the possible watchdog time range that can be achieved for different module clock frequencies . Some numbers are rounded to 3 significant digits. Table 24 Watchdog Time ...
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Universal Asynchronous Receiver/Transmitter The Universal Asynchronous Receiver/Transmitter (UART) provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit and receive simultaneously also receive-buffered, i.e., it can commence reception of a second byte before a previously received byte has ...
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Baud-Rate Generator The baud-rate generator is based on a programmable 8-bit reload value, and includes divider stages (i.e., prescaler and fractional divider) for generating a wide range of baud rates based on its input clock f FDM FDEN f ...
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BG The following formulas calculate the final baud rate without and with the fractional divider respectively: baud rate ---------------------------------------------------------------------------------- - where 2 = BRPRE × ...
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The fractional divider is enabled (fractional divider mode) and the corresponding parameter settings are shown. Table 27 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK BRPRE (2 ) 26.67 ...
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LIN Protocol The UART can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature provides the capability to detect the baud rate within LIN protocol using ...
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The break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. In the LIN communication, a slave task is required to be synchronized at the beginning of the protected identifier field of ...
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High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received ...
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Data is transmitted or received on lines TXD and RXD, which are normally connected to the pins MTSR (Master Transmit/Slave Receive) and MRST (Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master Serial Shift Clock) or input ...
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Timer 0 and Timer 1 Timers 0 and 1 are count-up timers which are incremented every machine cycle terms of the input clock, every 2 PCLK cycles. Timer 0 can also be incremented in response to a ...
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Timer 2 Timer 16-bit general purpose timer (THL2) that has two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode. If the prescalar is disabled, Timer 2 counts with an input ...
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Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and ...
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The block diagram of the CCU6 module is shown in address decoder T12 clock control start T13 interrupt control Figure 30 CCU6 Block Diagram Data Sheet Figure module kernel compare channel 0 1 dead- channel 1 time 1 control channel ...
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Analog-to-Digital Converter The XC864 includes a high-performance 8-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input ...
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ADC Clocking Scheme A common module clock f and digital parts of the ADC module: • input clock for the analog part. ADCA • internal clock for the analog part (defines the time base for ...
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Table 30 f Frequency Selection ADCI Module Clock f CTC ADC 26.7 MHz cannot exceed 10 MHz, bit field CTC should not be set to 00 ADCI 26.7 MHz. During slow-down mode where f ...
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On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • use the built-in debug functionality of the XC800 ...
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JTAG Module TMS Primary TCK Debug JTAG TDI Interface TDO NMI Report Suspend System Control Control Reset Clock - parts of OCDS Figure 33 OCDS Block Diagram 3.19.1 NMI-mode priority over Debug-mode While the core is in NMI-mode (after an ...
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Debug-Suspend of Timers During debugging (while in Monitor Mode) and the debug-suspend functionality is enabled (MMCR2.DSUSP = 1, default), timers in certain modules in XC864 can be suspended based on the settings of their corresponding module suspend bits in ...
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Also suspending the other timer-modules makes sense for debugging: once the application is not running, stopping counters helps for a more complete “freeze” of the device-status during a break. It must be noted, in XC864 all of the debug suspend ...
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Chip Identification Number The XC864 identity (ID) register is located at Page 1 of address B3 register However, for easy identification of product variants, the Chip H Identification Number, which is an unique number assigned to ...
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Electrical Parameters This chapter provides the characteristics of the electrical parameters which are implementation-specific for the XC864. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Chapter 4.2 4.1.1 ...
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Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC864 can be subjected to without permanent damage. Table 31 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with ...
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... PLL output clock. During normal operating mode, CPU clock SYS details. Data Sheet Symbol Limit Values min. 4.5 V DDP 3.0 V DDP V SS 2.3 V DDC SYS - -40 92 Electrical Parameters Unit Notes/ Conditions max. 5 MHz °C 85 SAF-XC864... °C 125 SAK-XC864... / 3. Refer to SYS V 1.1, 2009-03 XC864 Figure 23 for ...
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DC Parameters 4.2.1 Input/Output Characteristics Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter = 5V Range V DDP Output low voltage Output high voltage Input low voltage on port pins (all except P0.0 & P0.1) Input low voltage on ...
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Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter 2) Pull-down current 3) Input leakage current Overload current on any pin Absolute sum of overload currents Voltage on any pin V during power off DDP Maximum current per pin (excluding and ...
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Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Input low voltage on RESET pin Input low voltage on TMS pin Input high voltage on port pins (all except P0.0 & P0.1) Input high voltage on P0.0 & P0.1 Input high ...
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Table 33 Input/Output Characteristics (Operating Conditions apply) Parameter Maximum current into V DDP Maximum current out Not subjected to production test, verified by design/characterization. Hysteresis is implemented to avoid meta stable states and switching due to ...
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Supply Threshold Characteristics 5.0V VDDP 2.5V VDDC V DDCPOR Figure 34 Supply Threshold Parameters Table 34 Supply Threshold Parameters (Operating Conditions apply) Parameters V prewarning voltage DDC V brownout voltage in DDC 1) active mode RAM data retention voltage ...
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ADC Characteristics The values in the table below are given for an analog power supply between 4 5.5 V. The ADC can be used with an analog power supply down Note that in this ...
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Table 35 ADC Characteristics (Operating Conditions apply; Parameter Symbol Switched C AINSW capacitance at the analog voltage inputs Input resistance of R AREF the reference input Input resistance of R AIN the selected analog channel 1) TUE is tested at ...
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R EXT V C AIN EXT V AREF Figure 35 ADC Input Circuits 4.2.3.1 ADC Conversion Timing Conversion time ADC r = CTC + 2 for CTC = for CTC = 11 ...
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Power Supply Current Table 36 Power Supply Current Parameters (Operating Conditions apply range) V DDP Parameter = 5V Range V DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 1) I ...
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Table 38 Power Supply Current Parameters (Operating Conditions apply; = 3.3V range) V DDP Parameter = 3.3V Range V DDP Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 1) I The typical values are ...
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AC Parameters 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 36, Figure 37 V DDP 90% 10 Figure 36 Rise/Fall Time Parameters V DDP V DDE ...
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Output Rise/Fall Times Table 40 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter = 5V Range V DDP 1) 2) Rise/fall times = 3.3V Range V DDP 1)2) Rise/fall times 1) Rise/Fall time measurements are taken with 10% - ...
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Power-on Reset and PLL Timing VDDP V PAD VDDC t OSCST OSC PLL Flash State t RST RESET Pads 2) 1) 1)Pad state undefined I)until EVR is stable Figure 40 Power-on Reset Timing Table 41 Power-On Reset and PLL ...
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On-Chip Oscillator Characteristics Table 42 On-Chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol Nominal frequency f NOM ∆f Long term frequency 2) deviation ∆f Short term frequency deviation 1) Nominal condition 2 DDC 2) Not ...
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JTAG Timing Table 43 TCK Clock Timing (Operating Conditions apply; C Parameter TCK clock period TCK high time TCK low time TCK clock rise time TCK clock fall time 0.5 V DDP TCK Figure 41 TCK Clock Timing Data ...
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Table 44 JTAG Timing (Operating Conditions apply; C Parameter TMS setup to TCK TMS hold to TCK TDI setup to TCK TDI hold to TCK TDO valid output from TCK TDO high impedance to valid output from TCK TDO valid ...
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SSC Master Mode Timing Table 45 SSC Master Mode Timing (Operating Conditions apply; C Parameter SCLK clock period MTSR delay from SCLK MRST setup to SCLK MRST hold from SCLK 1/f . When f ...
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Package and Reliability 5.1 Package Parameters (PG-TSSOP-20) Table 46 provides the thermal characteristics of the package. Table 46 Thermal Characteristics of the Package Parameter Thermal resistance junction 1) case top Thermal resistance junction 1) case bottom 1) The top ...
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Package Outline Figure 43 PG-TSSOP-20 Package Outline Data Sheet Package and Reliability 111 XC864 V 1.1, 2009-03 ...
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Quality Declaration Table 47 shows the characteristics of the quality parameters in the XC864. Table 47 Quality Parameters Parameter ESD susceptibility according to Human Body Model (HBM) ESD susceptibility according to Charged Device Model (CDM) pins Data Sheet Symbol ...
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Data Sheet Package and Reliability 113 XC864 V 1.1, 2009-03 ...
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... Published by Infineon Technologies AG ...