M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 488
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Multiple Interrupts
Table 2.14.1. Settings of interrupt priority levels
Figure 2.14.4. Hardware interrupts priorities
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Interrupt priority
level select bit
(5) Interrupt Priority
0
0
0
1
1
1
1
b2 b1 b0
0
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt
in the following timing:
If there are two or more interrupt requests occurring at a point in time within a single sampling (check-
ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Figure 2.14.4 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
0
0
1
0
0
1
1
1
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
0
1
0
0
1
0
1
1
that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the
instruction used.
effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in
the instruction used.
_______
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
________
Interrupt priority
level
Priority
order
High
Low
Table 2.14.2. Interrupt levels enabled according
IPL
0
0
0
1
1
1
1
0
2
IPL
IPL
0
0
1
0
0
1
1
1
1
IPL
0
1
0
0
1
0
1
1
0
to the contents of the IPL
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt levels 1 and above are enabled
All maskable interrupts are disabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
Enabled interrupt priority levels
M16C / 62A Group
Mitsubishi microcomputers
2-169
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