M30620FCAFP#D3 Renesas Electronics America, M30620FCAFP#D3 Datasheet - Page 412
M30620FCAFP#D3
Manufacturer Part Number
M30620FCAFP#D3
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30620FCAFP#D3
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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UART
Figure 2.5.14. Operation timing of transmission in UART mode (used for SIM interface)
Transmit
enable bit (TE)
Signal line level
(Note 2)
Transfer clock
Transmit buffer
empty flag (Tl)
T
R
Transmit buffer
empty flag
(TEXPT)
Transmit
interrupt request
bit (IR)
X
X
Example of wiring
Example of operation (when direct format)
D
D
2
2
(Note 2)
(Note 2)
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: TxD
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,
the signal level resulting from connecting TxD
(1) Transmission enabled
2
and RxD
(2) Start transmission
Microcomputer
Start
ST
ST
Data is set in UART2 transmit buffer register
bit
2
are connected in the manner of wired OR as shown in the connection diagram. So TxD
D
D
0
0
D
D
1
1
Tc
RxD
D
D
TxD
2
2
D
D
3
3
D
D
2
4
4
2
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
5
5
D
D
6
6
Cleared to “0” when interrupt request is accepted, or cleared by software
2
D
D
Parity
7
7
and RxD
bit
Tc = 16 (n + 1) / fi
P
P
SP
SP
Stop
fi : frequency of BRG2 count source (f
n : value set to BRG2
(3) Confirme stop bit
bit
2
is shown as a signal line level.
(4) Start transmission
(Note 1)
ST
ST
Detects the level
using an interrupt
routine
Since a parity error occurred, the
“L” level returns from TxD
D
D
0
0
D
D
1
1
D
D
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
2
SIM card
D
D
3
3
D
D
4
4
1
D
D
, f
5
5
8
2
D
D
, f
6
6
32
)
D
D
7
7
2
and RxD
P
P
SP
M16C / 62A Group
SP
(5) Dispose
Mitsubishi microcomputers
parity error
2
ought to
Detects the level
using an interrupt
routine
2-93
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