HD6473258P10V Renesas Electronics America, HD6473258P10V Datasheet - Page 129

MCU 5V 32K PB-FREE 64-DIP

HD6473258P10V

Manufacturer Part Number
HD6473258P10V
Description
MCU 5V 32K PB-FREE 64-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/325r
Datasheets

Specifications of HD6473258P10V

Core Size
8-Bit
Program Memory Size
32KB (32K x 8)
Oscillator Type
External
Core Processor
H8/300
Speed
10MHz
Connectivity
SCI, UART/USART
Number Of I /o
53
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Operating Temperature
-20°C ~ 75°C
Package / Case
64-DIP
No. Of I/o's
53
Ram Memory Size
1024Byte
Cpu Speed
10MHz
No. Of Timers
3
Digital Ic Case Style
DIP
Supply Voltage
RoHS Compliant
Controller Family/series
H8/330
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Peripherals
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
600
Part Number:
HD6473258P10V
Manufacturer:
RENESAS
Quantity:
1 200
Part Number:
HD6473258P10V
Manufacturer:
HITACHI/日立
Quantity:
20 000
When the ISIE and LTE bits in the handshake control/status register (HCSR) are both set to 1, if a
high-to-low transition of the IS signal occurs during software standby mode, an input strobe
interrupt is requested and the chip recovers from software standby mode to handle the interrupt.
If the parallel handshaking interface is set for input, the port 3 input data are also latched.
If either the ISIE or LTE bit is cleared to 0, then high-to-low transitions of the IS signal are ignored
during software standby mode.
6.3.4 Sample Application
Figure 6-6 shows an example in which the parallel handshaking interface is used to interconnect
two H8/325 chips. Figure 6-7 shows the interface timing.
Port 3
Ø
OS
H8/325 (sending chip)
Figure 6-5. Output Strobe Timing in Software Standby Mode
Figure 6-6. Sample Usage of Parallel Handshaking Interface
Port 3 write
P3 to P3
7
OS
IS
0
T
1
Software
standby mode
Same data held
Same state held
120
Clock
settling time
H8/325 (receiving chip)
T
P3 to P3
IS
OS
2
T + T = 7 system clocks
1
7
2
0
Fig 6-5

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