DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 505

• Manufacturer Part Number: DF3052BX25V
• Description: MCU 5V 512K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3052BX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data
Figure 13.10 shows a sample flowchart for transmitting multiprocessor serial data and
indicates the procedure to follow.
Clear DR bit to 0, set DDR bit to 1
TDR and set MPBT bit in SSR
Figure 13.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit to 0 in SCR
Write transmit data in
Clear TDRE flag to 0
Output break signal?
All data transmitted?
Start transmitting
TDRE = 1?
TEND = 1?
Initialize
End
Yes
Yes
Yes
Yes
No
No
No
No
1
2
3
4
1. SCI initialization: the transmit data output
2. SCI status check and transmit data write:
3. To continue transmitting serial data: after
4. To output a break signal at the end of
function of the TxD pin is selected
automatically.
read SSR, check that the TDRE flag is 1,
then write transmit data in TDR. Also set
the MPBT flag to 0 or 1 in SSR. Finally,
clear the TDRE flag to 0.
checking that the TDRE flag is 1,
indicating that data can be written, write
data in TDR, then clear the TDRE flag to
0. When the DMAC is activated by a
transmit-data-empty interrupt request (TXI)
to write data in TDR, the TDRE flag is
checked and cleared automatically.
serial transmission: set the DDR bit to 1
and clear the DR bit to 0 (DDR and DR are
I/O port registers), then clear the TE bit to
0 in SCR.
Section 13 Serial Communication Interface
Rev. 3.00 Mar 21, 2006 page 475 of 814
REJ09B0302-0300