DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 107
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 107 of 847
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4.4
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in the instruction code.
4.5
Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7)
Legend:
PCE:
PCH:
PCL:
CCR:
SP:
Notes: 1.
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
2.
Trap Instruction
Stack Status after Exception Handling
PC indicates the address of the first instruction that will be executed after return.
Register saving and restoration must be carried out in word or longword size at even
addresses.
Before exception handling
Figure 4.6 Stack after Completion of Exception Handling
Stack area
Pushed on stack
SP (ER7)
SP+1
SP+2
SP+3
SP+4
Rev. 3.00 Mar 21, 2006 page 77 of 814
After exception handling
Section 4 Exception Handling
CCR
PC
PC
PC
E
H
L
REJ09B0302-0300
Even address
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