DF3052BX25V Renesas Electronics America, DF3052BX25V Datasheet - Page 127
DF3052BX25V
Manufacturer Part Number
DF3052BX25V
Description
MCU 5V 512K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3052BX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
Company:
Part Number:
DF3052BX25V
Manufacturer:
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Quantity:
10 000
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5.4
5.4.1
The H8/3052BF handles interrupts differently depending on the setting of the UE bit. When UE =
1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI
bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and
UI bits.
NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4
SYSCR
UE
1
0
UE = 1: Interrupts IRQ
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
Interrupt Operation
Interrupt Handling Process
I
0
1
0
1
UE, I, and UI Bit Settings and Interrupt Handling
CCR
UI
—
—
—
0
1
0
to IRQ
Description
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
No interrupts are accepted except NMI.
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
NMI and interrupts with priority level 1 are accepted.
No interrupts are accepted except NMI.
5
and interrupts from the on-chip supporting modules can all be
Rev. 3.00 Mar 21, 2006 page 97 of 814
Section 5 Interrupt Controller
REJ09B0302-0300
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