DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 318
DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
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Section 11 16-Bit Free-Running Timer (FRT)
11.3.1
FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and
CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to
H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit
units; cannot be accessed in 8-bit units. FRC is initialized to H'0000.
11.3.2
The FRT has two output compare registers, OCRA and OCRB, each of which is a 16-bit
readable/writable register whose contents are continually compared with the value in FRC. When
a match is detected (compare-match), the corresponding output compare flag (OCFA or OCFB) is
set to 1 in TCSR. If the OEA or OEB bit in TOCR is set to 1, when the OCR and FRC values
match, the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output
compare output pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0
until the first compare-match. OCR should always be accessed in 16-bit units; cannot be accessed
in 8-bit units. OCR is initialized to H'FFFF.
11.3.3
The FRT has four input capture registers, ICRA to ICRD, each of which is a 16-bit read-only
register. When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID)
is detected, the current FRC value is transferred to the corresponding input capture register (ICRA
to ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set
to 1. The FRC contents are transferred to ICR regardless of the value of ICF. The input capture
edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, by means of buffer
enable bits A and B (BUFEA and BUFEB) in TCR. For example, if an input capture occurs when
ICRC is specified as the ICRA buffer register, the FRC contents are transferred to ICRA, and then
transferred to the buffer register ICRC.
To ensure input capture, the input capture pulse width should be at least 1.5 system clocks ( ) for
a single edge. When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clocks ( ).
ICRA to ICRD should always be accessed in 16-bit units; cannot be accessed in 8-bit units. ICR is
initialized to H'0000.
Rev. 3.00 Mar 21, 2006 page 262 of 788
REJ09B0300-0300
Free-Running Counter (FRC)
Output Compare Registers A and B (OCRA, OCRB)
Input Capture Registers A to D (ICRA to ICRD)
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