DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 125
![IC H8S MCU FLASH 128K 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
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- Current page: 125 of 847
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3.3
3.3.1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries
bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.
3.3.2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.
Ports 1, 2 and A output an address by setting 1 to the corresponding port data direction register
(DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B
functions as a data bus when the ABW bit in WSCR is cleared to 0.
3.3.3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The
CPU can access a 56-kbyte address space in mode 3.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. Ports 1
and 2 function as an address bus by setting 1 to the corresponding port data direction register
(DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B
functions as a data bus when the ABW bit in WSCR is cleared to 0.
Mode 1
Mode 2
Mode 3
Operating Mode Descriptions
Rev. 3.00 Mar 21, 2006 page 69 of 788
Section 3 MCU Operating Modes
REJ09B0300-0300
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