COP8CCE9IMT7/NOPB National Semiconductor, COP8CCE9IMT7/NOPB Datasheet - Page 70

• Manufacturer Part Number: COP8CCE9IMT7/NOPB
• Description: MCU 8BIT FLASH 8K MEM 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8CCE9IMT7

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20.0 Instruction Set
20.6 INSTRUCTION SET SUMMARY
ADD
ADC
SUBC
AND
ANDSZ
OR
XOR
IFEQ
IFEQ
IFNE
IFGT
IFBNE
DRSZ
SBIT
RBIT
IFBIT
RPND
X
X
LD
LD
LD
LD
LD
X
X
LD
LD
LD
CLR
INC
DEC
LAID
DCOR
RRC
RLC
SWAP
SC
RC
IFC
IFNC
POP
PUSH
VIS
JMPL
JMP
JP
A,Meml
A,Meml
A,Meml
A,Meml
A,Imm
A,Meml
A,Meml
MD,Imm
A,Meml
A,Meml
A,Meml
#
Reg
#,Mem
#,Mem
#,Mem
A,Mem
A,[X]
A,Meml
A,[X]
B,Imm
Mem,Imm
Reg,Imm
A, [B
A, [X
A, [B
A, [X
[B
A
A
A
A
A
A
A
A
A
Addr.
Addr.
Disp.
±
],Imm
±
±
±
±
]
]
]
]
ADD
ADD with Carry
Subtract with Carry
Logical AND
Logical AND Immed., Skip if Zero
Logical OR
Logical EXclusive OR
IF EQual
IF EQual
IF Not Equal
IF Greater Than
If B Not Equal
Decrement Reg., Skip if Zero
Set BIT
Reset BIT
IF BIT
Reset PeNDing Flag
EXchange A with Memory
EXchange A with Memory [X]
LoaD A with Memory
LoaD A with Memory [X]
LoaD B with Immed.
LoaD Memory Immed.
LoaD Register Memory Immed.
EXchange A with Memory [B]
EXchange A with Memory [X]
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
CLeaR A
INCrement A
DECrement A
Load A InDirect from ROM
Decimal CORrect A
Rotate A Right thru C
Rotate A Left thru C
SWAP nibbles of A
Set C
Reset C
IF C
IF Not C
POP the stack into A
PUSH A onto the stack
Vector to Interrupt Service Routine
Jump absolute Long
Jump absolute
Jump relative short
(Continued)
70
A ← A + Meml
A ← A + Meml + C, C ← Carry,
HC ← Half Carry
A ← A − MemI + C, C ← Carry,
HC ← Half Carry
A ← A and Meml
Skip next if (A and Imm) = 0
A ← A or Meml
A ← A xor Meml
Compare MD and Imm, Do next if MD = Imm
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A ≠ Meml
Compare A and Meml, Do next if A
Do next if lower 4 bits of B ≠ Imm
Reg ← Reg − 1, Skip if Reg = 0
1 to bit, Mem (bit = 0 to 7 immediate)
0 to bit, Mem
If bit #,A or Mem is true do next instruction
Reset Software Interrupt Pending Flag
A
A
A ← Meml
A ← [X]
B ← Imm
Mem ← Imm
Reg ← Imm
A
A
A ← [B], (B ← B
A ← [X], (X ← X
[B] ← Imm, (B ← B
A ← 0
A ← A + 1
A ← A − 1
A ← ROM (PU,A)
A ← BCD correction of A (follows ADC, SUBC)
C → A7 → … → A0 → C
C ← A7 ← … ← A0 ← C, HC ← A0
A7…A4
C ← 1, HC ← 1
C ← 0, HC ← 0
IF C is true, do next instruction
If C is not true, do next instruction
SP ← SP + 1, A ← [SP]
[SP] ← A, SP ← SP − 1
PU ← [VU], PL ← [VL]
PC ← ii (ii = 15 bits, 0 to 32k)
PC9…0 ← i (i = 12 bits)
PC ← PC + r (r is −31 to +32, except 1)
↔
↔
↔
↔
Mem
[X]
[B], (B ← B
[X], (X ← X
↔
A3…A0
±
±
±
±
1)
1)
1)
1)
±
1)
>
Meml