COP8CCE9IMT7/NOPB National Semiconductor, COP8CCE9IMT7/NOPB Datasheet - Page 17

• Manufacturer Part Number: COP8CCE9IMT7/NOPB
• Description: MCU 8BIT FLASH 8K MEM 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8CCE9IMT7

9.0 Pin Descriptions
The COP8CBE/CCE I/O structure enables designers to re-
configure the microcontroller’s I/O functions with a single
instruction. Each individual I/O pin can be independently
configured as output pin low, output high, input with high
impedance or input with weak pull-up device. A typical ex-
ample is the use of I/O pins as the keyboard matrix input
lines. The input lines can be programmed with internal weak
pull-ups so that the input lines read logic high when the keys
are all open. With a key closure, the corresponding input line
will read a logic zero since the weak pull-up can easily be
overdriven. When the key is released, the internal weak
pull-up will pull the input line back to logic high. This elimi-
nates the need for external pull-up resistors. The high cur-
rent options are available for driving LEDs, motors and
speakers. This flexibility helps to ensure a cleaner design,
with less external components and lower costs. Below is the
general description of all available pins.
V
pins must be connected.
Users of the LLP package are cautioned to be aware that the
central metal area and the pin 1 index mark on the bottom of
the package may be connected to GND. See figure below:
CKI is the clock input. This can be connected (in conjunction
with CKO) to an external crystal circuit to form a crystal
oscillator. See Oscillator Description section.
RESET is the master reset input. See Reset description
section.
AV
connected to V
resistor ladder D/A converter used within the A/D converter.
AGND is the ground pin for the A/D converter. It should be
connected to GND externally. This is also the bottom of the
resistor ladder D/A converter used within the A/D converter.
The device contains up to six bidirectional 8-bit I/O ports (A,
B, G, H and L), where each individual bit may be indepen-
dently configured as an input (Schmitt trigger inputs on ports
L and G), output or TRI-STATE under program control. Three
data memory address locations are allocated for each of
these I/O ports. Each I/O port has three associated 8-bit
memory mapped registers, the CONFIGURATION register,
the output DATA register and the Pin input register. (See the
memory map for the various addresses associated with the
I/O ports.) Figure 3 shows the I/O port configurations. The
DATA and CONFIGURATION registers allow for each port bit
to be individually configured under software control as
CC
CC
and GND are the power supply pins. All V
is the Analog Supply for A/D converter. It should be
CC
externally. This is also the top of the
FIGURE 2.
20022570
CC
and GND
17
shown below:
Port A is an 8-bit I/O port. All A pins have Schmitt triggers on
the inputs. The 44-pin package does not have a full 8-bit port
and contains some unbonded, floating pads internally on the
chip. The binary value read from these bits is undetermined.
The application software should mask out these unknown
bits when reading the Port A register, or use only bit-access
program instructions when accessing Port A. These uncon-
nected bits draw power only when they are addressed (i.e.,
in brief spikes). Additionally, if Port A is being used with some
combination of digital inputs and analog inputs, the analog
inputs will read as undetermined values and should be
masked out by software.
Port A supports the analog inputs for the A/D converter. Port
A has the following alternate pin functions:
A7 Analog Channel 7
A6 Analog Channel 6
A5 Analog Channel 5
A4 Analog Channel 4
A3 Analog Channel 3
A2 Analog Channel 2
A1 Analog Channel 1
A0 Analog Channel 0
Port B is an 8-bit I/O port. All B pins have Schmitt triggers on
the inputs. If Port B is being used with some combination of
digital inputs and analog inputs, the analog inputs will read
as undetermined values. The application software should
mask out these unknown bits when reading the Port B
register, or use only bit-access program instructions when
accessing Port B.
Port B supports the analog inputs for the A/D converter. Port
B has the following alternate pin functions:
B7 Analog Channel 15 or A/D Input
B6 Analog Channel 14 or Analog Multiplexor Output
B5 Analog Channel 13 or Analog Multiplexor Output
B4 Analog Channel 12
B3 Analog Channel 11
B2 Analog Channel 10
B1 Analog Channel 9
B0 Analog Channel 8
Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O
ports. Pin G6 is always a general purpose Hi-Z input. All pins
have Schmitt Triggers on their inputs. Pin G1 serves as the
dedicated WATCHDOG output with weak pull-up if the
WATCHDOG feature is selected by the Option register.
The pin is a general purpose I/O if WATCHDOG feature is
not selected. If WATCHDOG feature is selected, bit 1 of the
Port G configuration and data register does not have any
effect on Pin G1 setup. G7 serves as the dedicated output
pin for the CKO clock output.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin, the associated bits in the data and configu-
CONFIGURATION
Register
0
0
1
1
Register
DATA
0
1
0
1
Hi-Z Input
(TRI-STATE Output)
Input with Weak Pull-Up
Push-Pull Zero Output
Push-Pull One Output
Port Set-Up
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