COP8CCE9IMT7/NOPB National Semiconductor, COP8CCE9IMT7/NOPB Datasheet - Page 22

• Manufacturer Part Number: COP8CCE9IMT7/NOPB
• Description: MCU 8BIT FLASH 8K MEM 48-TSSOP
• Manufacturer: National Semiconductor
• Series: COP8™ 8Cr

Specifications of COP8CCE9IMT7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TSSOP
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Data Ram Size: 256 B
• On-chip Adc: 10 bit, 16 channel
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Height: 0.9 mm
• Interface Type: SPI, USART
• Length: 12.5 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 6.1 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8CCE9IMT7

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10.0 Functional Description
10.7 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Brownout Reset is activated.
The following occurs upon initialization:
(Continued)
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port H: TRI-STATE (High Impedance Input)
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T2CNTRL: CLEARED
Port G: TRI-STATE (High Impedance Input). Exceptions: If
Watchdog is enabled, then G1 is Watchdog output. G0
and G2 have their weak pull-up enabled during RESET.
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
FIGURE 8. Reset Logic
20022511
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HSTCR: CLEARED
ITMR: Cleared except Bit 6 (HSON) = 1
Accumulator, Timer 1 and Timer 2:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
S Register: CLEARED
RAM:
USART:
ANALOG TO DIGITAL CONVERTER:
ISP CONTROL:
RANDOM after RESET
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit
which is set to one.
ENAD: CLEARED
ADRSTH: RANDOM
ADRSTL: RANDOM
ISPADLO: CLEARED
ISPADHI: CLEARED
PGMTIM: PRESET TO VALUE FOR 10 MHz CKI