MC68HC711E9MFNE2 Freescale Semiconductor, MC68HC711E9MFNE2 Datasheet - Page 218

• Manufacturer Part Number: MC68HC711E9MFNE2
• Description: IC MCU 8BIT 512BYTES ROM 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9MFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog-to-Digital (A/D) Converter
10.10 A/D Control/Status Register
Technical Data
218
Address:
All bits in this register can be read or written, except bit 7, which is a
read-only status indicator, and bit 6, which always reads as 0. Write to
ADCTL to initiate a conversion. To quit a conversion in progress, write to
this register and a new conversion sequence begins immediately.
CCF — Conversion Complete Flag
Bit 6 — Unimplemented
SCAN — Continuous Scan Control Bit
MULT — Multiple Channel/Single Channel Control Bit
Reset:
Read:
Write:
A read-only status indicator, this bit is set when all four A/D result
registers contain valid conversion results. Each time the ADCTL
register is overwritten, this bit is automatically cleared to 0 and a
conversion sequence is started. In the continuous mode, CCF is set
at the end of the first conversion sequence.
Always reads 0
When this control bit is clear, the four requested conversions are
performed once to fill the four result registers. When this control bit is
set, conversions are performed continuously with the result registers
updated as data becomes available.
When this bit is clear, the A/D converter system is configured to
perform four consecutive conversions on the single channel specified
by the four channel select bits CD:CA (bits [3:0] of the ADCTL
register). When this bit is set, the A/D system is configured to perform
$1030
Figure 10-5. A/D Control/Status Register (ADCTL)
CCF
Bit 7
0
Analog-to-Digital (A/D) Converter
= Unimplemented
6
0
SCAN
5
MULT
4
Indeterminate after reset
CD
3
M68HC11E Family — Rev. 3.2
CC
2
CB
1
MOTOROLA
Bit 0
CA