M30800SFP-BL#U5 Renesas Electronics America, M30800SFP-BL#U5 Datasheet - Page 41

MCU 3/5V 0K,PB-FREE 100-QFP

M30800SFP-BL#U5

Manufacturer Part Number
M30800SFP-BL#U5
Description
MCU 3/5V 0K,PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet

Specifications of M30800SFP-BL#U5

Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30800SFP-BL#U5M30800SFP-BL#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30800SFP-BL#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M
R
R
e
E
1
v
J
Figure 6.2 Processor mode register 1
6
1 .
0
C
9
0 .
8 /
B
Processor mode register 1 (Note 1) :Mask ROM version
Processor mode register 1 (Note 1) :Flash memory version
0
0
0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
1
A
8
G
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
Note 1: Set bit 1 of the protect register (address 000A
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
Note 1: Set bit 1 of the protect register (address 000A
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
Note 5: Rewrite this bit when the main clock is in division by 8 mode.
2
0
0
0
0
5
Page 28
Nothing is assinged. When read, the content is indeterminate.
Reserved bit
Reserved bit
Reserved bit
Bit symbol
Bit symbol
PM12
PM12
PM14
PM15
PM10
PM11
PM14
PM15
PM10
PM11
f o
Symbol
PM1
Symbol
PM1
3
2
9
3
3
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Internal memory wait bit
ALE pin select bit (Note 3)
Internal memory wait bit
ALE pin select bit (Note 3)
External memory area
mode bit (Note 3)
External memory area
mode bit (Note 3)
Address
Address
0005
Bit name
0005
Bit name
ROMless version (144-pin version)
16
16
16
16
) to “1” when writing new values to this register.
) to “1” when writing new values to this register.
When reset
When reset
b5 b4
b5 b4
0 0 : No ALE
0 1 : P5
1 0 : P5
1 1 : P5
0 0 : No ALE
0 1 : P5
1 0 : P5
1 1 : P5
b1 b0
b1 b0
0 0 : Mode 0 (P4
0 1 : Mode 1 (P4
1 0 : Mode 2 (P4
1 1 : Mode 3 (Note 2)
0 0 : Mode 0 (P4
0 1 : Mode 1 (P4
1 0 : Mode 2 (P4
1 1 : Mode 3 (Note 2)
Must always be set to “0”
Must always be set to “1” (Note 5)
0 : No wait state
1 : Wait state inserted
0 : No wait state
1 : Wait state inserted
Must always be set to “0”
00
00
16
16
(P4
(P4
3
6
4
3
6
4
/BCLK (Note 4)
/RAS
/HLDA
/BCLK (Note 4)
/RAS
/HLDA
4
4
to P4
to P4
P4
P4
P4
P4
Function
Function
7
7
4
4
5
5
4
4
4
4
6
: CS3 to CS0)
6
: CS3 to CS0)
: A
, P4
: A
, P4
to P4
, P4
to P4
, P4
to P4
to P4
20
20
5
5
7
7
,
,
7
7
: A
: A
: CS1, CS0)
: CS1, CS0)
7
7
: CS2 to CS0)
: CS2 to CS0)
: A
: A
6. Processor Mode
20
20
20
20
, A
, A
to A
to A
21
21
,
,
23
23
)
)
R
R
W
W

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