HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 880
HD64F2338VFC25
Manufacturer Part Number
HD64F2338VFC25
Description
MCU 3V 256K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of HD64F2338VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F2338VFC25
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.1.2
The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration.
Table 20.1 Clock Pulse Generator Register
Name
System clock control register
Note: * Lower 16 bits of the address.
20.2
20.2.1
SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode
in which the bus master runs on a medium-speed clock and the other supporting modules run on
the high-speed clock, and a function that allows the medium-speed mode to be disabled and the
clock division ratio to be changed for the entire chip.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Bit 6—Reserved: This bit can be read or written to, but only 0 should be written.
Rev.4.00 Sep. 07, 2007 Page 848 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Register Configuration
Register Descriptions
System Clock Control Register (SCKCR)
Normal Operation
φ output (Initial value)
Fixed high
:
:
PSTOP
R/W
7
0
R/W
—
6
0
Abbreviation
SCKCR
Sleep Mode
φ output
Fixed high
R/W
DIV
5
0
Description
—
—
4
0
R/W
R/W
Software
Standby Mode
Fixed high
Fixed high
—
—
0
3
Initial Value
H'00
SCK2
R/W
2
0
Hardware
Standby Mode
High impedance
High impedance
SCK1
R/W
1
0
Address *
H'FF3A
SCK0
R/W
0
0
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