HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 575

• Manufacturer Part Number: HD64F2338VFC25
• Description: MCU 3V 256K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2338VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3
11.3.1
PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set
to 1. In this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating
conditions.
Table 11.3 PPG Operating Conditions
NDER
0
1
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the
next compare match. For details of non-overlapping operation, see section 11.3.4, Non-
Overlapping Pulse Output.
Pulse output pin
Operation
Overview
1
1
DDR
0
0
Generic output port
compare match occurs, the NDR bit value is transferred to the PODR bit)
PPG pulse output
Pin Function
Generic input port
Generic input port (but the PODR bit is a read-only bit, and when
DDR
Q
Figure 11.2 PPG Output Operation
Normal output/inverted output
Q
NDER
Q
PODR
C
Output trigger signal
Rev.4.00 Sep. 07, 2007 Page 543 of 1210
D
Q
NDR
D
REJ09B0245-0400
Internal data bus