HD64F2338VFC25 Renesas Electronics America, HD64F2338VFC25 Datasheet - Page 316

Manufacturer Part Number

HD64F2338VFC25

MCU 3V 256K 144-QFP

Manufacturer

Renesas Electronics America

H8® H8S/2300r

Core Processor

Connectivity

SCI, SmartCard

DMA, POR, PWM, WDT

Number Of I /o

Program Memory Size

256KB (256K x 8)

Program Memory Type

Voltage - Supply (vcc/vdd)

2.7 V ~ 3.6 V

Data Converters

A/D 12x10b; D/A 4x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Manufacturer

BOSTOCK HK LIMITED

Part Number:

HD64F2338VFC25

Manufacturer:

Renesas Electronics America

There can be no break between a DMA cycle read and a DMA cycle write. This means that a

refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read

and external write in a DMA cycle.

In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh

or external bus released state may be inserted after a write cycle. Since the DTC has a lower

priority than the DMAC, the DTC does not operate until the DMAC releases the bus.

When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these

DMA cycles can be executed at the same time as refresh cycles or external bus release. However,

simultaneous operation may not be possible when a write buffer is used.

Rev.4.00 Sep. 07, 2007 Page 284 of 1210

REJ09B0245-0400

Relation Between the DMAC and External Bus Requests, Refresh Cycles, and the