MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 592
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
To prepare the QADC for a scan sequence, write to the CCW table to specify the desired channel
conversions. The criteria for queue execution is established by selecting the queue operating mode. The
queue operating mode determines what type of trigger event starts queue execution. A trigger event refers
to any of the ways that cause the QADC to begin executing the CCWs in a queue or subqueue. An external
trigger is only one of the possible trigger events.
A scan sequence may be initiated by:
The queue can be scanned in single pass or continuous fashion. When a single-scan mode is selected, the
scan must be engaged by setting the single-scan enable bit. When a continuous-scan mode is selected, the
queue remains active in the selected queue operating mode after the QADC completes each queue scan
sequence.
During queue execution, the QADC reads each CCW from the active queue and executes conversions in
three stages:
28-54
•
•
•
•
•
•
A software command
Expiration of the periodic/interval timer
An external trigger signal
An external gated signal (queue 1 only)
Initial sample
Final sample
00
63
P — Pause after Conversion
BYP — Bypass Buffer Amplifier
IST — Input Sample Time
CHAN — Channel Number and
Conversion Command
Beginning of Queue 1
Beginning of Queue 2
9
P
Word (CCW) Table
End of Queue 1
End of Queue 2
10-bit Conversion Command
until Next Trigger
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
BYP
8
Figure 28-43. QADC Conversion Queue Operation
End-of-Queue Code
•
•
•
•
•
•
Word Format
[7:6]
IST
CHAN
[5:0]
Channel Select,
A/D Conversion
Sample, Hold,
15 14 13 12 11 10
S
0
0 0 0 0 0
Right-Justified, Unsigned Result
Left-Justified, Unsigned Result
Left-Justified, Signed Result
RESULT
10-bit Result, Readable in
[15:6]
RESULT
[15:6]
Three 16-BIT Formats
Result Word Table
0
0
RESULT
0 0 0 0 0
0 0 0 0 0
[9:0]
•
•
•
•
•
•
[5:0]
[5:0]
Freescale Semiconductor
00
63
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