MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 410
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MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 410 of 766
- Download datasheet (9Mb)
Queued Serial Peripheral Interface (QSPI)
22.3.3
The QSPI wrap register provides halt transfer control, wraparound settings, and queue pointer locations.
22.3.4
The QIR contains QSPI interrupt enables and status flags.
22-6
IPSBAR
NEWQP
ENDQP
IPSBAR
CPTQP
WREN
WRTO
Offset:
Field
HALT
CSIV
11–8
Offset:
Reset
7–4
3–0
Reset
15
14
13
12
W
W
R
R
0x00_0348 (QWR)
0x00_034C (QIR)
WCEFB ABRTB
HALT WREN WRTO CSIV
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands after it has completed execution
of the current command.
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.
This field is read only.
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.
15
0
15
0
QWR[NEWQP] and continue execution.
a transfer (that is, inactive state is 0, chip selects are active high).
a transfer (that is, inactive state is 1, chip selects are active low).
QSPI Wrap Register (QWR)
QSPI Interrupt Register (QIR)
14
0
14
0
13
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
13
0
0
ABRTL WCEFE ABRTE
12
0
12
0
Figure 22-6. QSPI Interrupt Register (QIR)
Figure 22-5. QSPI Wrap Register (QWR)
Table 22-5. QWR Field Descriptions
11
0
11
0
10
0
ENDQP
10
0
0
9
Description
0
0
9
0
8
SPIFE
0
8
7
0
0
0
7
0
6
CPTQP
0
0
6
0
5
0
0
5
0
4
0
0
4
WCEF ABRT
w1c
Freescale Semiconductor
0
3
0
3
Access: User read/write
Access: User read/write
w1c
NEWQP
0
2
0
2
0
1
0
0
1
SPIF
w1c
0
0
0
0
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