MCF5216CVF66J Freescale Semiconductor, MCF5216CVF66J Datasheet - Page 459
MCF5216CVF66J
Manufacturer Part Number
MCF5216CVF66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.2.4
I2SR contains bits that indicate transaction direction and status.
Freescale Semiconductor
MSTA
TXAK
RSTA
Field
MTX
IIEN
IEN
7
6
5
4
3
2
1
IPSBAR
IPSBAR
Offset:
Offset:
Reset:
Reset:
I
transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.
Master mode is not aware that the bus is busy; initiating a start cycle may corrupt the current bus cycle, ultimately
causing the current master or the I
0 The I
1 The I
I
0 I
1 I
Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.
0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.
1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.
Transmit/receive mode select bit. Selects the direction of master and slave transfers.
0 Receive
1 Transmit. When the device is addressed as a slave, software must set MTX according to I2SR[SRW]. In master
Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for master and
slave receivers. Writing TXAK applies only when the I
0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
1 No acknowledge signal response is sent (acknowledge bit = 1).
Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.
0 No repeat start
1 Generates a repeated START condition.
Reserved, must be cleared.
W
2
2
R
C enable. Controls the software reset of the entire I
C interrupt enable.
mode, MTX must be set according to the type of transfer required. Therefore, when the MCU addresses a slave
device, MTX is always 1.
I
2
2
0x00_0308 (I2CR)
2
0x00_030C (I2SR)
C module interrupts are disabled, but currently pending interrupt condition is not cleared.
C module interrupts are enabled. An I
C Status Register (I2SR)
2
2
ICF
C module is disabled, but registers can be accessed.
C module is enabled. This bit must be set before any other I2CR bits have any effect.
0
1
7
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
IAAS
6
0
6
0
Figure 24-4. I
Figure 24-5. I
Table 24-4. I2CR Field Descriptions
2
C module to lose arbitration, after which bus operation returns to normal.
IBB
0
0
5
5
2
C interrupt occurs if I2SR[IIF] is also set.
2
2
C Control Register (I2CR)
C Status Register (I2SR)
IAL
0
0
4
4
Description
2
2
C module. If the module is enabled in the middle of a byte
C bus is a receiver.
0
0
0
3
3
SRW
0
0
2
2
Access: User read/write
Access: User read/write
IIF
0
0
1
1
RXAK
I
2
0
1
0
0
C Interface
24-5
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