M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 36

IC 740 MCU ROM 16K 42SSOP

M38513E4FP#U0

Manufacturer Part Number
M38513E4FP#U0
Description
IC 740 MCU ROM 16K 42SSOP
Manufacturer
Renesas Electronics America
Series
740/38000r
Datasheets

Specifications of M38513E4FP#U0

Core Processor
740
Core Size
8-Bit
Speed
8MHz
Connectivity
SIO, UART/USART
Peripherals
PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
42-SSOP
Package
42SSOP
Family Name
740
Maximum Speed
8 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
34
Interface Type
I2C-BUS
On-chip Adc
5-chx10-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
0035
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion
[AD Control Register (ADCON)] 0034
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
Channel Selector
The channel selector selects one of ports P3
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
Fig. 38 Block diagram of A-D converter
SS
and V
16
, 0036
REF
IN
) to 500 kHz or more during an A-D conversion.
into 1024 and outputs the divided voltages.
16
AD control register
P3
P3
P3
P3
P3
(Address 0034
1
2
3
4
0
/AN
/AN
/AN
/AN
/AN
1
2
3
4
0
16
)
0
/AN
0
Comparator
to P3
b7
3
16
4
/AN
4
A-D control circuit
and
Data bus
A-D conversion low-order register
A-D conversion high-order register
Resistor ladder
V
Fig. 36 Structure of AD control register
Fig. 37 Structure of A-D conversion registers
REF
Note : The high-order 6 bits of address 0036
b7
10-bit reading
8-bit reading (Read only address 0035
AV
10
(Read address 0036
(Address 0036
(Address 0035
(Address 0035
SS
b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
at reading.
MITSUBISHI MICROCOMPUTERS
16
16
16
A-D interrupt request
b0
)
)
)
(Address 0036
(Address 0035
b7
b7
b7
b7 b6 b5 b4 b3 b2 b1 b0
b9 b8 b7 b6 b5 b4 b3 b2
AD control register
(ADCON : address 0034
Not used (returns “0” when read)
A-D conversion completion bit
Analog input pin selection bits
Not used (returns “0” when read)
16
(Built-in 16 KB ROM)
b2 b1 b0
before 0035
0 0 0: P3
0 0 1: P3
0 1 0: P3
0 1 1: P3
1 0 0: P3
0: Conversion in progress
1: Conversion completed
3851 Group
0
1
2
3
4
16
16
/AN
/AN
/AN
/AN
/AN
16
)
)
become “0”
0
1
2
3
4
16
b9
16
)
16
)
)
b8
b0
b0
b0
33

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