M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 23

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MULTI-MASTER I
The multi-master I
cuit, conforming to the Philips I
interface, offering both arbitration lost detection and a synchro-
n o u s f u n c t i o n s , i s u s e f u l f o r t h e m u l t i - m a s t e r s e r i a l
communications.
Figure 19 shows a block diagram of the multi-master I
terface and Table 4 lists the multi-master I
functions.
This multi-master I
register, the I
the I
condition control register and other control circuits.
When using the multi-master I
more to .
Note: Mitsubishi Electric Corporation assumes no responsibility for in-
Fig. 19 Block diagram of multi-master I
20
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I
an I
2
C control register, the I
fringement of any third-party’s rights or originating in the use of the
connection control function between the I
ports SCL
ter (002E
2
C system, provided that the system conforms to the I
S e r i a l d a t a
( S
S2D
D A
2
16
1
C data shift register, the I
)
S e r i a l
c l o c k
( S
, SCL
).
SIS
C L
I
2
2
C start/stop condition
)
C-BUS interface is a serial communications cir-
2
SIP
2
C-BUS interface consists of the I
, SDA
control register
SSC4 S S C 3 S S C 2 S S C 1 S S C 0
2
C-BUS INTERFACE
1
N o i s e
e l i m i n a t i o n
c i r c u i t
Noise
elimination
circuit
and SDA
2
C status register, the I
2
2
C-BUS data transfer format. This
C-BUS interface, set 1 MHz or
2
with the bit 6 of I
2
C l o c k
c o n t r o l
c i r c u i t
C clock control register,
2
2
C-BUS interface
C-BUS interface and the
Data
control
circuit
2
circuit
c i r c u i t
C-BUS interface
B B
AL
2
C control regis-
2
S0D
2
2
C start/stop
I
2
C Standard Specification as defined by Philips.
2
2
C components conveys a license under the Philips I
C clock control register
C address
b7
C-BUS in-
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 S A D 0 RWB
A C K
S2
b7
b 7
S
0
A C K
B I T
Address comparator
I
2
MODE
I
FAST
C data shift register
2
C address register
C C R 4 CCR3 CCR2 C C R 1 CCR0
C l o c k d i v i s i o n
Table 4 Multi-master I
SCL clock frequency
System clock
Communication mode
Format
Item
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
b 0
b0
System clock ( )
Internal data bus
= f(X
= f(X
MITSUBISHI MICROCOMPUTERS
IN
IN
MST T R X B B P I N
S1D I C control register
2
b 7
S 1
b 7
T I S S
C-BUS interface functions
)/2 (high-speed mode)
)/8 (middle-speed mode)
In conformity with Philips I
standard:
In conformity with Philips I
standard:
16.1 kHz to 400 kHz (at = 4 MHz)
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Master transmission
Master reception
Slave transmission
Slave reception
CLK
STP
2
2
Interrupt
generating
circuit
C Patent Rights to use these components
1 0 B I T
S A D
(Built-in 16 KB ROM)
I
2
A L S
C clock control register
ES0
AL AAS AD0 LRB
Function
I
2
3851 Group
C status register
I n t e r r u p t r e q u e s t s i g n a l
( I I C I R Q )
B C 2 B C 1 B C 0
S 1 D
B i t c o u n t e r
b 0
2
2
b 0
C-BUS
C-BUS