M38513E4FP#U0 Renesas Electronics America, M38513E4FP#U0 Datasheet - Page 14

• Manufacturer Part Number: M38513E4FP#U0
• Description: IC 740 MCU ROM 16K 42SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38513E4FP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 42-SSOP
• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

INTERRUPTS
Interrupts occur by 16 sources among 16 sources: seven external,
eight internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
2. The interrupt disable flag is set and the corresponding interrupt
3. The interrupt jump destination address is read from the vector
register are automatically pushed onto the stack.
request bit is cleared.
table into the program counter.
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
•When switching interrupt sources of an interrupt vector address
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Related register: Interrupt edge selection register (address 3A
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit or the interrupt source select bit.
Set the corresponding interrupt request bit to “0” after 1 or more
Set the corresponding interrupt enable bit to “1” (enabled).
instructions have been executed.
Notes
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer XY mode register (address 23
MITSUBISHI MICROCOMPUTERS
(Built-in 16 KB ROM)
3851 Group
16
)
16
16
11
)
)