MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 47

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68331TS/D
MOVE from CCR
MOVE from SR
MOVE to CCR
DIVSL/DIVUL
MOVE to SR
EORI to CCR
MOVE USP
EORI to SR
Instruction
DIVS/DIVU
LPSTOP
ILLEGAL
MOVEA
MOVEC
MOVEM
MOVEA
CMPM
MOVE
CMP2
EXTB
DBcc
EORI
EOR
EXG
LINK
JMP
EXT
JSR
LEA
LSR
LSL
1
1
1
1
1
1
1
# <data>, <ea>
# <data>, CCR
(An) , (An)
<ea>, Dr : Dq
<ea>, Dr : Dq
# <data>, SR
# <data>, Dn
#<data>, Dn
<ea>, <ea>
CCR, <ea>
<ea>, CCR
SR, <ea>
<ea>, SR
<ea>, Rn
<ea>, Dn
<ea>, Dq
Dn, <ea>
<ea>, An
<ea>, An
list, <ea>
<ea>, list
Dn, label
# <data>
USP, An
An, USP
USP, An
An, USP
Syntax
Rn, Rn
An, # d
Dn, Dn
Dn, Dn
Rc, Rn
Rn, Rc
none
<ea>
<ea>
<ea>
<ea>
Freescale Semiconductor, Inc.
Table 20 Instruction Set Summary (Continued)
Dn
Dn
Dn
For More Information On This Product,
Go to: www.freescale.com
32/16
64/32
32/32
Operand Size
16, 32
16, 32
32/32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
8
16, 32
16, 32
none
none
none
16
16
32
32
16
16
16
32
32
16
16
16
16
32
32
32
32
8
16 : 16 Destination / Source
32 : 32
32 : 32
16
32
32
32
32
32
(Destination
Lower bound
If condition false, then Dn
if Dn
(signed or unsigned)
Destination / Source
(signed or unsigned)
Source
Data
Source
Source
Rn
Sign extended Destination
Sign extended Destination
SSP
SSP
SSP
Illegal instruction vector address
Destination
SP
<ea>
SP
Data
Source
Source
USP
An
CCR
Source
SR
Source
USP
An
Rc
Rn
Listed registers
Source
4
4
USP
USP
Rn
Rn
Rc
Destination
0
2
4
2
( 1), then PC
Destination
An
An
SR; interrupt mask
Destination
An
X/C
Destination
CCR
SR
SP; PC
SP, An
Destination
Destination
CCR
SR
Listed registers
SSP; vector offset
SSP; PC
SSP; SR
Source), CCR shows results
PC
Rn
SR
CCR
Destination
(SP); SP
Upper bound, CCR shows result
(SP); destination
Operation
Destination
d
Destination
Destination
(SSP);
(SSP);
Destination
1
PC
Destination
Destination
EBI; STOP
PC;
An, SP
(SSP);
PC
PC
X/C
d
0
SP
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