MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 46

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.6 Instruction Set Summary
46
ANDI to SR1
ANDI to CCR
Instruction
ABCD
ADDQ
BCHG
BGND
CMPA
ADDA
ADDX
BCLR
CHK2
BKPT
BSET
BTST
ADDI
ANDI
CMPI
ADD
AND
CHK
CMP
ASR
BRA
BSR
CLR
ASL
Bcc
1
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, <ea>
# <data>, CCR
#<data>, <ea>
# <data>, SR
# <data>, Dn
# <data>, Dn
(An),
(An),
Dn, <ea>
<ea>, Dn
<ea>, An
<ea>, Dn
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
Dn, <ea>
<ea>, Dn
<ea>, Rn
<ea>, Dn
<ea>, An
# <data>
Syntax
Dn, Dn
Dn, Dn
Dn, Dn
Dn, Dn
<ea>
<ea>
none
<ea>
label
label
label
Freescale Semiconductor, Inc.
For More Information On This Product,
(An)
(An)
Table 20 Instruction Set Summary
Go to: www.freescale.com
Operand Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
16, 32
16, 32
8, 32
8, 32
8, 32
8, 32
none
none
8, 32
8, 32
8, 32
8, 32
16
16
16
8
8
8
Source
Source
Source
Immediate data
Immediate data
Source
Source Destination
Data Destination
Source CCR
Source SR
If condition true, then PC
bit number of destination
0
If background mode enabled, then enter background
mode, else format/vector
PC
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal instruction
PC
1
SP
If Dn < 0 or Dn > (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0
(Destination
(Destination
(Destination
bit number of destination
bit number of destination
bit number of destination
Z
bit of destination
bit of destination
Destination
d
4
10
X/C
(SSP); SR
Destination
Destination
Destination
SP; PC
PC
Destination
Source), CCR shows results
Source), CCR shows results
Data), CCR shows results
SR
CCR
Destination
Destination
(SP); PC
Operation
Destination
10
X
Destination
(SSP); (vector)
Destination
Destination
d
X
Destination
(SSP);
PC
Destination
d
Z
Destination
Destination
Z;
Z
PC
bit of destinatio
MC68331TS/D
X/C
PC
0