MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 41

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.8.2 Interrupt Processing Summary
3.9 Factory Test Block
SIMTR — System Integration Module Test Register
SIMTRE — System Integration Module Test Register (E Clock)
TSTMSRA — Master Shift Register A
TSTMSRB — Master Shift Register B
TSTSC — Test Module Shift Count
TSTRC — Test Module Repetition Count
CREG — Test Module Control Register
DREG — Test Module Distributed Register
MC68331TS/D
service request has been detected and is pending.
A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt
The test submodule supports scan-based testing of the various MCU modules. It is integrated into the
SIM to support production testing.
Test submodule registers are intended for Motorola use. Register names and addresses are provided
to indicate that these addresses are occupied.
A. The CPU finishes higher priority exception processing or reaches an instruction boundary.
B. Processor state is stacked. The contents of the status register and program counter are saved.
C. The interrupt acknowledge cycle begins:
D. Modules or external peripherals that have requested interrupt service decode the request level
E. After arbitration, the interrupt acknowledge cycle can be completed in one of three ways:
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor transfers control to
1. FC[2:0] are driven to %111 (CPU space) encoding.
2. The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16] = %1111,
3. Request priority level is latched into the IP field in the status register from the address bus.
in ADDR[3:1]. If the request level of at least one interrupting module or device is the same as
the value in ADDR[3:1], interrupt arbitration contention takes place. When there is no conten-
tion, the spurious interrupt monitor asserts BERR, and a spurious interrupt exception is pro-
cessed.
1. The dominant interrupt source supplies a vector number and DSACK signals appropriate
2. The AVEC signal is asserted (the signal can be asserted by the dominant interrupt source
3. The bus monitor asserts BERR and the CPU32 generates the spurious interrupt vector
the exception handler routine.
which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4]
= %111111111111; ADDR[3:1] = the level of the interrupt request being acknowledged;
and ADDR0 = %1.
to the access. The CPU32 acquires the vector number.
or the pin can be tied low), and the CPU32 generates an autovector number corresponding
to interrupt priority.
number.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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