MCF5216CVM66J Freescale Semiconductor, MCF5216CVM66J Datasheet - Page 36
MCF5216CVM66J
Manufacturer Part Number
MCF5216CVM66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 36 of 766
- Download datasheet (9Mb)
Overview
1-4
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— Toggle-on-overflow feature for pulse-width modulator (PWM) generation
— One dual-mode pulse accumulation channel per timer
Four periodic interrupt timers (PITs)
— 16-bit counter
— Selectable as free running or count down
Software watchdog timer
— 16-bit counter
— Low-power mode support
Phase locked loop (PLL)
— Crystal or external oscillator reference
— 2- to 10-MHz reference frequency for normal PLL mode
— 33- to 80-MHz (66 MHz for MCF5214/16) oscillator reference frequency for 1:1 mode
— Low-power modes supported
— Separate clock output pin
Two interrupt controllers
— Support for up to 63 interrupt sources per interrupt controller (a total of 126), organized as
— Seven external interrupt signals
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low-power modes
DMA controller
— Four fully programmable channels
— Dual-address transfer support with 8-, 16- and 32-bit data capability along with support for
— Source/destination address pointers that can increment or remain constant
— 24-bit byte transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Software-programmable connections between the 11 DMA requesters in the UARTs (3), 32-bit
External bus interface
— Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.)
— SDRAM controller supports 8-, 16-, and 32-bit wide memory devices
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 32-bit bidirectional data bus
— 24-bit address bus
— Up to seven chip selects available
— Byte/write enables (byte strobes)
follows:
– 56 fully-programmable interrupt sources
– 7 fixed-level interrupt sources
16-byte (4 x 32-bit) burst transfers
timers (4) plus external logic (4) and the four DMA channels
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor
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