MCF5216CVM66J Freescale Semiconductor, MCF5216CVM66J Datasheet - Page 11
MCF5216CVM66J
Manufacturer Part Number
MCF5216CVM66J
Description
IC MCU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5216CVM66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5216CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.4 Prioritization Between Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5 Low-Power Wakeup Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Low-Power Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.3 Interrupt/General-Purpose I/O Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Chip Select Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.3 Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4 Chip Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Freescale Semiconductor
10.3.1 Interrupt Pending Registers (IPRHn, IPRLn) . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.2 Interrupt Mask Register (IMRHn, IMRLn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn) . . . . . . . . . . . . . . . . . . . . 10-9
10.3.4 Interrupt Request Level Register (IRLRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) . . . . . . . . . 10-11
10.3.6 Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)) . . . . . . . . . . . . . . . . . . . 10-12
10.3.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) . . . . . 10-16
11.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
12.3.1 General Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.4.1 Chip Select Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
10.1.1.1 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.1.1.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.1.1.3 Interrupt Vector Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.3.6.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
11.4.2.1 EPORT Pin Assignment Register (EPPAR) . . . . . . . . . . . . . . . . . . . 11-3
11.4.2.2 EPORT Data Direction Register (EPDDR) . . . . . . . . . . . . . . . . . . . . 11-4
11.4.2.3 Edge Port Interrupt Enable Register (EPIER) . . . . . . . . . . . . . . . . . . 11-5
11.4.2.4 Edge Port Data Register (EPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.4.2.5 Edge Port Pin Data Register (EPPDR) . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.4.2.6 Edge Port Flag Register (EPFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
12.3.1.1 8-, 16-, and 32-Bit Port Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3.1.2 External Boot Chip Select Operation . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.4.1.1 Chip Select Address Registers (CSAR0–CSAR6) . . . . . . . . . . . . . . 12-6
12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6) . . . . . . . . . . . . . . . . 12-6
12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6) . . . . . . . . . . . . . . . 12-7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Edge Port Module (EPORT)
Chip Select Module
Chapter 11
Chapter 12
xi
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