DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 79

• Manufacturer Part Number: DF36054FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
Input/output
Pin state
PCR5
PDR5
RAM0
Input/output
Pin state
PCR5
PDR5
BSET
MOV.B
MOV.B
BSET instruction executed
After executing BSET instruction
Prior to executing BCLR instruction
Bit Manipulation in a Register Containing a Write-Only Bit
#0,
@RAM0, R0L
R0L,
P57
Input
Low
level
0
1
1
P57
Input
Low
level
0
1
@PDR5
@RAM0
0
0
0
0
0
P56
Input
High
level
P56
Input
High
level
P55
Output
Low
level
1
0
0
P55
Output
Low
level
1
0
The BSET instruction is executed designating the PDR5
work area (RAM0).
The work area (RAM0) value is written to PDR5.
P54
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
Rev. 4.00 Mar. 15, 2006 Page 45 of 556
P52
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
REJ09B0026-0400
Section 2 CPU
P50
Output
High
level
1
1
1
P50
Output
Low
level
1
0