DF36054FPJV Renesas Electronics America, DF36054FPJV Datasheet - Page 389

• Manufacturer Part Number: DF36054FPJV
• Description: MCU 3/5V 32K J-TEMP PB-FREE 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36054FPJV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.4
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Bit
2
1
0
Bit
7
6
5
4
3
2
Bit Name
CKS2
CKS1
CKS0
Bit Name
TE
RE
RSSTP
—
TEIE
TIE
SS Enable Register (SSER)
Initial
Value
0
0
0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Description
Transfer clock rate select
Sets transfer clock rate (prescaler division ratio) when the
internal clock is selected.
000: /256
001: /128
010: /64
011: /32
100: /16
101: /8
110: /4
111: Reserved
Description
Transmit enable
When this bit is 1, transmit operation is enabled.
Receive enable
When this bit is 1, receive operation is enabled.
Receive single stop
When this bit is 1, receive operation is completed after
receiving one byte.
Reserved
This bit is always read as 0.
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 355 of 556
REJ09B0026-0400